Semiconductor Gate Structure CESL Removal for Fabrication Efficiency
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Solution Overview
Problem
The conventional polysilicon gate in semiconductor fabrication faces issues such as boron penetration and depletion, leading to inferior device performance, and the removal of the contact etch stop layer (CESL) between gate structures is a costly and complex process in high-k metal transistor fabrication.
Innovation Solution
A method involving the formation of a substrate with gate structures, deposition of a CESL, selective etching to remove part of the CESL between gate structures, and subsequent formation of an interlayer dielectric (ILD) layer, which simplifies the process and eliminates the need for an extra step to remove CESL during contact plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an extra step is added to remove part of the CESL during contact plug formation, then the device performance is improved, but the fabrication cost and process complexity increase
Solution Approach 1:
The patent applies preliminary action by removing the CESL between gate structures before forming the ILD layer, rather than removing it later during contact plug formation. This advance removal eliminates the need for an extra processing step later in the fabrication sequence, thereby reducing overall process complexity while maintaining the necessary device performance improvements
Solution Approach 2:
The patent segments the CESL removal operation into a distinct preliminary step performed between gate structures, separating it from the main contact plug formation process. This segmentation allows the CESL removal to be integrated into the existing fabrication flow without requiring additional equipment or process modules, thus improving device performance without proportionally increasing complexity
2Reliability
If an extra step is added to remove part of the CESL during contact plug formation, then the device performance is improved, but the fabrication cost increases
Solution Approach 1:
By performing CESL removal as a preliminary action before ILD formation, the patent eliminates the need for a separate, costly extra step during contact plug formation. This timing optimization allows standard fabrication equipment and processes to be used throughout, avoiding the need for additional specialized processing that would increase manufacturing costs
Solution Approach 2:
The patent merges the CESL removal operation with the existing ILD formation process by performing the removal beforehand. This consolidation integrates what would otherwise be a separate, additional process step into the normal fabrication flow, thereby achieving the necessary device performance improvement without adding discrete manufacturing cost centers
3Ease of manufacture
If the CESL is removed between gate structures, then the contact plug formation is simplified, but the CESL integrity on top of gate structures must be maintained
Solution Approach 1:
The patent applies local quality by selectively removing the CESL only in the regions between gate structures while preserving the CESL on top of the gate structures themselves. This localized removal approach uses targeted etching or removal processes that affect only specific areas, thereby simplifying contact plug formation in the inter-gate regions without compromising the CESL's protective or structural function on the gate structures
Solution Approach 2:
The patent segments the CESL into functionally distinct regions: one that is removed between gates to simplify contact formation, and one that is retained on top of gates to maintain integrity. This spatial segmentation allows different portions of the same layer to serve different purposes in the fabrication process, achieving both simplified contact plug formation and preserved CESL integrity where needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by eliminating the need for an additional processing step, reducing fabrication complexity and cost, and maintaining the integrity of the CESL on top of gate structures while removing it between them, thus improving the overall semiconductor device fabrication efficiency.
Implementation Method 1
removing part of the CESL between the first gate structure and the second gate structure
Implementation Method 2
forming an interlayer dielectric (ILD) layer on the CESL
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.