Dual-Well Field Effect Diode for ESD Protection
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Solution Overview
Problem
Existing ESD protection circuits for semiconductor devices, particularly in SOI technology, face challenges with high leakage current, high capacitive loading, and limited ESD capability due to self-heating, which complicates protection at advanced process nodes like 65 nm and beyond.
Innovation Solution
A dual-well field effect diode (DW-FED) structure is implemented, comprising a silicon substrate with P+-type and N+-type regions separated by N-well and P-well regions, and a gate electrode overlying these regions, allowing for series-coupled diodes that behave as two forward-biased diodes in normal conditions and short as a single diode during ESD events, reducing leakage and capacitive loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are used in SOI technology, then ESD protection is provided, but high leakage current and high capacitive loading occur
Solution Approach 1:
The ESD protection circuit is segmented into two series-coupled diodes (first diode and second diode) instead of using a single diode. This segmentation allows the circuit to maintain low leakage current and low capacitive loading during normal operation while providing effective ESD protection when activated
Solution Approach 2:
The circuit dynamically changes its behavior based on operating conditions. During normal operation, both diodes are forward-biased and block current flow. During an ESD event, one diode becomes reverse-biased and conducts current, while the other remains forward-biased, creating a low-impedance path for ESD current
2Loss of energy
If thin SOI films are used to reduce leakage and capacitive loading, then leakage and capacitive loading are reduced, but ESD capability is limited due to high self-heating
Solution Approach 1:
The invention uses a dual-well structure (N-well and P-well regions) within the SOI film, adding a vertical dimension to the device architecture. This allows the thin SOI film to provide low leakage and capacitive loading while the dual-well configuration distributes heat generation and maintains ESD capability
3Loss of energy
If series-coupled diodes are used in normal operation, then low leakage and capacitive loading are achieved, but device size may increase
Solution Approach 1:
The first diode and second diode are merged into a single integrated structure with shared regions (the N-well and P-well regions are shared between the two diodes). This merging reduces the overall device area compared to using two separate diodes, while maintaining the low leakage and capacitive loading characteristics of the series-coupled configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DW-FED structure effectively protects semiconductor structures from ESD events by maintaining low leakage and capacitive loading, enabling efficient ESD protection with reduced size and enhanced ESD capability, suitable for high-speed I/O pads and local clamping circuits.
Implementation Method 1
forward biasing the first diode and the second diode
Implementation Method 2
shorting out the first diode or the second diode in the event of an electrostatic discharge event
Implementation Method 3
a gate electrode is disposed at least substantially overlying the N-well and P-well device regions of the silicon substrate
Data Source
AI summary
Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.