Flash Memory Cells With Deep Trench Isolation For Efficient Programming
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Solution Overview
Problem
Existing flash memory devices face inefficiencies in programming due to high power consumption, as only a small fraction of electrons injected into the floating gate result in data storage, leading to excessive drain current requirements.
Innovation Solution
The implementation of dielectrically isolated memory cells with deep trench isolation structures allows for forward-bias write operations, enabling more efficient electron injection into charge-storage nodes by isolating memory cells and optimizing the conductivity types of the upper and buried wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hot-electron injection is used for programming flash memory cells, then data storage capability is achieved, but power consumption increases due to excessive drain current requirements
Solution Approach 1:
The invention segments the semiconductor substrate into multiple isolated regions using deep trench isolation structures. Each region contains memory cells that are electrically isolated from adjacent regions, enabling independent programming operations. This segmentation allows for reduced drain current requirements in each isolated region while maintaining data storage capability, thereby reducing overall power consumption.
Solution Approach 2:
The invention applies different conductivity types to different regions of the semiconductor substrate through the deep trench isolation structures. By creating regions with specific conductivity characteristics (n-type or p-type) isolated from each other, the device optimizes local electrical properties to enhance programming efficiency and reduce power consumption while maintaining reliable data storage.
2Productivity
If deep trench isolation structures with different conductivity types are implemented, then programming efficiency is enhanced, but device complexity increases
Solution Approach 1:
The deep trench isolation structures divide the semiconductor substrate into discrete, isolated regions. Each region can be independently programmed with specific conductivity types (n-type or p-type), enhancing programming efficiency by allowing targeted electron or hole injection. The segmentation enables parallel processing of multiple regions, improving overall productivity while the modular nature of the isolation structures helps manage device complexity.
Solution Approach 2:
The invention changes the electrical parameters of different regions by implementing deep trench isolation structures with varying conductivity types. By controlling the doping concentrations and conductivity types in isolated regions, the device optimizes programming efficiency for different memory cell types. This parameter control enables enhanced productivity while the systematic approach to parameter variation helps manage structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances programming efficiency by improving the ratio of gate current to drain-source current, allowing for more effective data storage with reduced power dissipation.
Implementation Method 1
Programming efficiency in flash memory, which is defined as a ratio of transistor gate current to programming drain-source current, is an important factor in determining power consumption in flash memories. The programming efficiency of flash memory cells, which utilize hot-electron injection, has been enhanced by applying a substrate bias.
Implementation Method 2
The implementation of dielectrically isolated memory cells with deep trench isolation structures allows for forward-bias write operations, enabling more efficient electron injection into charge-storage nodes by isolating memory cells and optimizing the conductivity types of the upper and buried wells.
Data Source
AI summary
A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.