Semiconductor Gate Spacer Suppresses Hot-Electron Punchthrough
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties due to hot-electron-induced punchthrough (HEIP) phenomena, resulting in reduced effective channel length and increased leakage current.
Innovation Solution
A semiconductor device design incorporating a device isolation layer, first and second gate electrodes, and a gate spacer, where the gate spacer is positioned between the gate electrodes and the boundary between the active region and the device isolation layer, preventing channel formation at this boundary and thus reducing current flow and HEIP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOS-FETs are scaled down to reduce pattern size, then device density increases, but operational properties deteriorate due to HEIP phenomena
Solution Approach 1:
The gate structure is segmented into a first gate electrode on the active region and a second gate electrode on the device isolation layer, with a gate spacer between them. This segmentation prevents channel formation at the boundary between active region and device isolation layer, suppressing HEIP phenomena while maintaining scaled-down dimensions
Solution Approach 2:
A gate spacer is introduced as an intermediary element between the first gate electrode and the second gate electrode. This gate spacer prevents direct channel formation at the critical boundary region between active region and device isolation layer, thereby suppressing hot-electron-induced punchthrough while allowing continued scaling
2Length of moving object
If gate electrodes are positioned close to the boundary between active region and device isolation layer, then effective channel length is reduced, but leakage current increases due to HEIP
Solution Approach 1:
The gate spacer acts as an intermediary that prevents channel formation at the boundary between active region and device isolation layer. This eliminates the HEIP effect and associated leakage current while preserving the shortened effective channel length between source and drain regions
Solution Approach 2:
The gate structure has different configurations at different locations: the first gate electrode is positioned on the active region away from the boundary, while the second gate electrode is positioned on the device isolation layer. This local differentiation suppresses HEIP at the boundary while maintaining effective channel control in the active region
Data Source
AI summary
A semiconductor device includes device isolation layer on a substrate to define an active region, a first gate electrode on the active region extending in a first direction parallel to a top surface of the substrate, a second gate electrode on the device isolation layer and spaced apart from the first gate electrode in the first direction, a gate spacer between the first gate electrode and the second gate electrode, and source/drain regions in the active region at opposite sides of the first gate electrode. The source/drain regions are spaced apart from each other in a second direction that is parallel to the top surface of the substrate and crossing the first direction, and, when viewed in a plan view, the first gate electrode is spaced apart from a boundary between the active region and the device isolation layer.