Semiconductor Wiring Segmentation for ESD Reduction
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Solution Overview
Problem
Existing semiconductor devices are prone to damage from electrostatic discharge (ESD) due to charge accumulation in long lead wirings exposed to a plasma atmosphere, leading to potential short-circuits and damage to transistors and insulating layers during manufacturing processes.
Innovation Solution
The formation of a semiconductor device with a series connection of island-shaped wirings, where the second and third island-shaped wirings are electrically connected through openings in the second insulating layer, reducing the surface area exposed to the plasma and minimizing charge accumulation, thereby reducing the likelihood of ESD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long lead wirings are used in display devices, then electrical connection is achieved, but charge accumulation occurs when exposed to plasma atmosphere causing ESD damage
Solution Approach 1:
The patent divides the long lead wiring into multiple separate wirings (first wiring, second wiring, third wiring) that are electrically connected through insulating layers. This segmentation reduces the continuous surface area exposed to plasma, thereby minimizing charge accumulation while maintaining electrical connectivity across the display device.
Solution Approach 2:
The patent implements a nested structure where wirings are embedded within insulating layers. The first wiring is covered by a first insulating layer, which is then covered by a second insulating layer containing the second wiring, which is in turn covered by a third insulating layer containing the third wiring. This nesting protects wirings from plasma exposure while maintaining electrical connections.
2Ease of manufacture
If wirings are exposed to plasma atmosphere for manufacturing steps, then processing is completed, but charge accumulation leads to ESD damage
Solution Approach 1:
The patent embeds wirings within multiple insulating layers during manufacturing, creating a nested structure that allows plasma processing to be performed on outer layers without directly exposing inner wirings to plasma. This maintains manufacturing feasibility while protecting against charge accumulation.
Solution Approach 2:
The patent segments the wiring structure into multiple separate conductive elements connected through insulating barriers. This segmentation allows plasma processing to be performed on specific areas without exposing entire wiring paths, reducing overall charge accumulation while maintaining manufacturing capability.
3Reliability
If insulating layer thickness is reduced, then device performance is enhanced, but ESD damage risk increases
Solution Approach 1:
The patent divides the electrical connection path into multiple segments separated by insulating layers. Even though individual insulating layers are thin for performance, the cumulative effect of multiple layers provides enhanced ESD protection by creating multiple barriers to charge discharge paths.
Solution Approach 2:
The nested arrangement of multiple insulating layers with embedded wirings creates a multi-layered protection structure. Each insulating layer acts as a barrier, and the nested configuration ensures that charge accumulation is distributed and blocked at multiple levels, protecting against ESD even when individual layer thickness is minimized for performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the occurrence of ESD in semiconductor devices during manufacturing, preventing damage to transistors and insulating layers, and enhances the reliability and performance of the semiconductor device by minimizing charge accumulation and maintaining a reduced insulating layer thickness.
Implementation Method 1
When the long lead wiring in a floating state (an electrically isolated state) is exposed to a plasma atmosphere, charge is easily accumulated
Implementation Method 2
ESD is caused by the charge accumulated in the wiring
Data Source
AI summary
A semiconductor device is provided in which ESD is less likely to occur in a manufacturing process thereof. In manufacture of a semiconductor device including a long lead wiring A, during steps with direct exposure to a plasma atmosphere, a plurality of island-shaped wirings is formed for the wiring A and then electrically connected to one another in series. Specifically, a plurality of island-shaped wirings is formed, covered with an insulating layer, and electrically connected to one another in series by a wiring formed over the insulating layer. The island-shaped wiring and the wiring formed over the insulating layer are electrically connected to each other through an opening formed in the insulating layer.