FinFET Via Formation With Etch Stop Layer

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Solution Overview

Problem

During via formation in semiconductor manufacturing, the etching process can lead to overconsumption of nitride layers, resulting in varying via depths and increased contact resistance due to uneven etching rates, which complicates the formation of consistent metal contact interfaces.

Innovation Solution

Incorporating a first etch stop layer with high etching selectivity between nitride layers to arrest the etching process, ensuring uniform via depth and preventing overetching, thereby maintaining a consistent contact interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching time is extended to ensure complete via formation, then via depth uniformity improves, but nitride layer overconsumption increases

Engineering Contradiction:
Improvevia depth uniformityVSAvoidnitride layer overconsumption
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

An etch stop layer is introduced as an intermediary between the nitride layers. This etch stop layer has high etching selectivity, meaning it etches much slower than the nitride layers. During the etching process, the etch stop layer acts as a mediator that arrests the etching at a controlled depth, preventing overetching of the nitride layers while ensuring uniform via formation. The etch stop layer is consumed at a controlled rate, allowing precise control of via depth and nitride layer consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of substance

If etching time is reduced to prevent nitride layer overconsumption, then nitride layer preservation improves, but contact resistance increases due to smaller contact interface

Engineering Contradiction:
Improvenitride layer preservationVSAvoidcontact resistance
Core Design Contradiction:
Loss of substanceVSReliability

Solution Approach 1:

The etch stop layer serves as a mediator that enables precise control of etching depth. By having high etching selectivity, it allows the etching process to stop at the desired depth before consuming excessive nitride layers, while still achieving sufficient via depth for good metal contact interface and low contact resistance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The etching selectivity parameter is optimized by choosing appropriate etch stop layer materials and etching conditions. This parameter change allows differential etching rates that preserve nitride layers while achieving the necessary via depth for low contact resistance.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If etching speed is increased to improve productivity, then manufacturing efficiency improves, but via formation uniformity deteriorates due to varying etching rates across different locations

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidvia formation uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etch stop layer acts as a mediator that uniformizes the etching process across different locations. Its high etching selectivity creates a consistent arrest point for the etching process, ensuring that vias formed at different locations have uniform depth and quality, even when etching speeds vary across the wafer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures uniform via formation and reduces contact resistance by controlling the etching process, ensuring consistent via depth and interface quality across the semiconductor device.

Implementation Method 1

Incorporating a first etch stop layer with high etching selectivity between nitride layers to arrest the etching process

Methodology Applied
Scientific EffectEtching selectivity:

Data Source

PatentUS10157844B2FinFET device having oxide layer among interlayer dielectric layer
Publication Date: 2018.12.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10157844B2 patent drawing
  • US10157844B2 patent drawing
  • US10157844B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate having a fin structure. A gate structure is disposed over the fin structure. A first dielectric layer is disposed on the gate structure and the fin structure. A contact plug is disposed in the first dielectric layer and electrically connected to source/drain region in the fin structure. A second dielectric layer is disposed on the first dielectric layer. the second dielectric layer has a first nitride layer and a first etch stop layer, and the first nitride layer is disposed on the first etch stop layer. A via goes through the second dielectric layer and electrically connected to the contact plug. A metal layer is disposed on the second dielectric layer.