Angled Local Interconnects for Self-Aligned Semiconductor Contacts
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Solution Overview
Problem
Existing interconnection methods in semiconductor devices, such as up-and-over and wrap-around connections, face challenges with lithographic constraints, placement errors, and are not well-suited for tight pitch/scaled dimensions, leading to reliability and manufacturing issues.
Innovation Solution
The use of angled local interconnects and jogged vias that extend laterally between adjacent conductive structures, formed using directional etches, to create self-aligned connections within the device layer, reducing the need for complex patterning and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If up-and-over or wrap-around interconnections are used, then connections between transistor contacts can be established, but lithographic constraints and placement errors increase, and reliability decreases for tight pitch/scaled dimensions
Solution Approach 1:
The patent transitions from planar interconnections to three-dimensional angled interconnections. The local interconnect extends laterally from the source/drain contact and angles upward to meet the gate contact, utilizing the vertical dimension to achieve direct connections without requiring precise lateral alignment across multiple layers. This dimensional change eliminates the need for complex up-and-over or wrap-around routing.
Solution Approach 2:
The angled local interconnect structure is self-aligned to the gate contact through the angling process itself. The lateral extension from the source/drain contact automatically positions the interconnect to meet the gate contact without requiring additional alignment steps or complex lithographic patterning, making the structure self-positioning and reducing manufacturing complexity.
2Device complexity
If traditional interconnection methods are used, then connections can be made, but the number of interconnect layers above the device layer increases, leading to increased device complexity and capacitance
Solution Approach 1:
The patent extracts the interconnection function from the traditional multi-layer interconnect structure and implements it locally within the device layer. By forming the angled local interconnect directly at the transistor level, the need for additional interconnect layers above the device layer is eliminated, simplifying the overall device structure and reducing parasitic capacitance.
3Productivity
If conventional interconnection approaches are used, then transistor connections can be established, but transistor density and performance are limited due to the complexity of interconnect routing
Solution Approach 1:
By utilizing the vertical angle rather than lateral routing, the patent enables direct connections between source/drain and gate contacts without requiring additional lateral space for complex routing paths. This allows transistors to be placed closer together, increasing transistor density while maintaining simple interconnect routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves transistor density, performance, and reliability by reducing the number of interconnects above the device layer, minimizing defects, and lowering production costs, while also reducing capacitance and complexity.
Implementation Method 1
an angled local interconnect portion formed by removing material using a directional etch
Data Source
AI summary
In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.