Surrounding Gate Transistor NOR Circuit Area Reduction
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Solution Overview
Problem
Conventional semiconductor devices with planar transistors require significant area due to the need for well isolation and body terminals, which limits their compactness and efficiency.
Innovation Solution
The use of surrounding gate transistors (SGTs) arranged in a specific configuration with silicon pillars and silicide layers to form NOR circuits, eliminating the need for well isolation and body terminals, allowing for a more compact and efficient layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar transistors with well isolation and body terminals are used, then transistor isolation and potential application are ensured, but device area increases significantly
Solution Approach 1:
The invention extracts and removes the well isolation structure and body terminals from the transistor design. By using surrounding gate transistors where the gate electrode completely surrounds the semiconductor layer, the patent eliminates the need for separate well isolation regions and body terminal connections, thereby reducing device area while maintaining transistor isolation through the gate structure itself
Solution Approach 2:
The surrounding gate structure serves multiple functions simultaneously: it provides the gate function for transistor operation, ensures isolation between transistors of different types, and eliminates the need for separate body terminal connections. This multi-functionality reduces the overall device area by consolidating multiple required structures into a single integrated gate configuration
2Area of stationary object
If surrounding gate transistors are used to eliminate well isolation and body terminals, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The invention transitions from a planar two-dimensional transistor structure to a three-dimensional surrounding gate structure. The gate electrode is positioned above and surrounds the semiconductor layer in the vertical dimension, creating a wrap-around configuration that provides complete gate control while simplifying the overall device layout by eliminating lateral well isolation structures
3Ease of manufacture
If conventional planar transistor layout is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
By moving to a three-dimensional surrounding gate configuration, the patent achieves higher integration density by utilizing vertical space above the substrate. The gate electrode wraps around the semiconductor layer from above, allowing transistors to be packed more densely in the planar direction while maintaining proper electrical isolation and control through the vertical gate structure
Data Source
AI summary
A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit.