NMOS Substrate Bias Pump for ESD Protection and Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing integrated circuit designs, such as grounded gate N channel MOSFETs, suffer from unacceptably high parasitic capacitance, which hampers their performance in high frequency and high speed applications due to slowed switching speed, making them unsuitable for radio frequency applications.
Innovation Solution
Incorporating a substrate bias pump that applies a steady state direct current negative bias to the back gate of an NMOS transistor, reducing capacitance and enhancing switching speed, allowing the use of GGNMOS devices in high speed applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a grounded gate N channel MOSFET is used for electrostatic discharge protection, then electrostatic discharge handling capability is improved, but parasitic capacitance increases to unacceptably high levels
Solution Approach 1:
The patent applies substrate biasing to dynamically change the electrical parameters of the MOSFET. By applying a negative bias to the substrate, the threshold voltage is adjusted and the parasitic capacitance is reduced, allowing the device to meet both ESD protection requirements and high-speed performance specifications
2Reliability
If a grounded gate N channel MOSFET is used for electrostatic discharge protection, then electrostatic discharge handling capability is improved, but switching speed decreases to unacceptably low rates
Solution Approach 1:
The substrate bias pump dynamically adjusts the substrate voltage parameter to optimize device performance. During normal operation, a negative substrate bias reduces the parasitic capacitance and increases switching speed. During ESD events, the bias is adjusted to maintain protection capability
3Speed
If substrate bias pump is applied to reduce capacitance, then switching speed is improved, but device complexity increases
Solution Approach 1:
The substrate bias pump is designed to operate autonomously, generating the required substrate bias voltage from the available power supplies without requiring external control circuitry. The pump circuit self-regulates to provide the appropriate bias conditions for both normal operation and ESD protection modes
Solution Approach 2:
The substrate bias pump serves multiple functions simultaneously: it reduces parasitic capacitance for high-speed operation, maintains ESD protection capability, and does so using standard MOSFET structures and available power supplies, thereby reducing overall system complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitance, thereby increasing switching speed and enabling the use of GGNMOS devices in high speed applications, such as radio frequency operations, while maintaining effective electrostatic discharge protection.
Implementation Method 1
A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation
Data Source
AI summary
An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.