GaN Device Structure With Composite Thermal Dielectric Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
GaN power transistors fabricated on silicon substrates face limitations in breakdown voltage and thermal dissipation, with silicon substrates offering poor thermal conductivity and high operational temperatures leading to device failure, while alternative substrates like diamond or sapphire provide high thermal conductivity but at increased costs and processing complexities.
Innovation Solution
A nitride semiconductor device structure where a GaN epi-layer stack is sandwiched between a thick dielectric header and a thin composite thermal dielectric layer, comprising a high dielectric strength polymer and a thermally conductive filler, to enhance breakdown voltage and thermal dissipation, while maintaining compatibility with conventional epitaxial growth on low-cost silicon substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN devices are fabricated on silicon substrates, then production costs are reduced, but breakdown voltage and thermal dissipation are limited
Solution Approach 1:
The patent uses a composite substrate structure combining silicon carbide (SiC) and gallium nitride (GaN) layers. The SiC layer provides high breakdown voltage capability and thermal conductivity, while the GaN layer enables low-cost fabrication processes. This composite approach allows the device to achieve high breakdown voltage (>1000V) while maintaining cost-effectiveness through standard GaN-on-SiC epitaxial growth techniques.
2Ease of manufacture
If GaN devices are fabricated on silicon substrates, then production costs are reduced, but thermal dissipation is poor leading to high operational temperatures
Solution Approach 1:
The SiC/GaN composite substrate leverages the superior thermal conductivity of silicon carbide (approximately 3-5 times higher than silicon) to efficiently conduct heat away from the active device regions. This enables effective thermal management while maintaining the cost advantages of fabricating on silicon-based substrates using conventional epitaxial growth methods.
3Temperature
If alternative substrates like diamond or sapphire are used, then thermal conductivity is improved, but costs and processing complexities increase
Solution Approach 1:
Instead of using expensive diamond or sapphire substrates throughout the entire device structure, the patent applies SiC specifically where thermal management and breakdown voltage are critical (the substrate and lower buffer regions), while using GaN where the active transistor functionality is required. This localized application of high-performance materials achieves the necessary thermal and electrical performance without the prohibitive costs of full diamond or sapphire construction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves increased vertical breakdown resistance and effective thermal dissipation, improving device performance and reducing operational temperatures, while maintaining cost-effectiveness and compatibility with existing silicon substrate technologies.
Implementation Method 1
an underlying, relatively thin composite thermal dielectric layer... effective thermal dissipation
Implementation Method 2
a GaN die... sandwiched between an overlying header... and an underlying composite thermal dielectric layer... increased vertical breakdown resistance
Data Source
AI summary
Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.