Semiconductor Manufacturing Process Integration for MOS Transistor and Capacitor
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Solution Overview
Problem
The existing methods for manufacturing semiconductor circuit devices with MOS transistors and capacitor elements require an increased number of steps, leading to higher manufacturing costs and potential electrostatic discharge protection capability deterioration when using LDD structures.
Innovation Solution
A method that forms a gate insulating film, patterns polysilicon films for both the MOS transistor and capacitor elements, and performs high concentration impurity implantations to reduce resistance simultaneously for both the gate and source/drain regions, allowing the capacitor element to be added without additional dedicated steps and enabling the formation of conventional-type MOS transistors without additional steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor element is added to a semiconductor circuit device using method B (polysilicon films for both electrodes), then the fixation of potential and generation of junction capacitance are avoided, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines the capacitor element manufacturing process with the existing MOS transistor manufacturing process by using the same polysilicon films and implantation steps. The lower electrode of the capacitor is formed using the same polysilicon film and implantation process as the MOS transistor gate electrode, merging two functions into a single process flow.
Solution Approach 2:
The polysilicon film serves multiple functions: it acts as the gate electrode for the MOS transistor and simultaneously as the lower electrode for the capacitor element. The implantation process also serves dual purposes by forming both the MOS transistor source/drain regions and the capacitor lower electrode in the same step.
2Manufacturing precision
If high concentration impurity implantation is performed separately for capacitor lower electrode resistance reduction, then the resistance is reduced, but the number of steps and manufacturing cost increase
Solution Approach 1:
The patent merges the implantation step for MOS transistor source/drain region formation with the implantation step for capacitor lower electrode resistance reduction. A single high concentration impurity implantation process achieves both objectives simultaneously, eliminating the need for a separate dedicated implantation step for the capacitor electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of manufacturing steps and manufacturing costs while maintaining or improving electrostatic discharge protection capabilities by integrating the capacitor element with the MOS transistor, allowing for efficient production of semiconductor circuit devices with reduced complexity.
Implementation Method 1
implanting high concentration impurities for reduction in resistance of a gate electrode and source and drain regions
Data Source
AI summary
Provided is a method of manufacturing a semiconductor circuit device including a MOS transistor and a capacitor element in which a gate electrode of a MOS transistor is formed of a first polysilicon film, a capacitor is formed of the first polysilicon film, a capacitor film, and a second polysilicon film, reduction in resistance of a normally-off transistor and reduction in resistance of a lower electrode of the capacitor are simultaneously performed, and reduction in resistance of an N-type MOS transistor and reduction in resistance of an upper electrode of the capacitor are simultaneously performed.