Amorphous Silicon Joining Member for 3D NAND Stacked Memory
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently manufacturing three-dimensionally stacked memory cell transistors for NAND flash memory, particularly in ensuring reliable electrical connections and precise etching processes to maintain device performance and reliability.
Innovation Solution
The semiconductor memory device employs a configuration with multiple stacked bodies and layers, including semiconductor layers, wiring layers, memory films, and insulating layers, with a conductive joining member and cover layers to facilitate electrical connections and precise etching, using amorphous silicon for the joining and cover layers to maintain etching selection ratios and protect memory films during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple stacked bodies are used to form three-dimensionally stacked memory cell transistors, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into multiple stacked bodies (first stacked body and second stacked body), each containing memory cell transistors arranged in three dimensions. This segmentation allows independent fabrication and assembly of each stacked body, reducing overall manufacturing complexity while increasing storage capacity through vertical stacking.
Solution Approach 2:
The patent employs a nested structure where first and second stacked bodies are positioned adjacent to each other, with semiconductor layers and wiring layers nested within each stacked body. The joining member connects these nested structures, enabling compact three-dimensional integration that increases storage capacity without proportionally increasing manufacturing complexity.
2Reliability
If joining members are used to connect semiconductor layers across stacked bodies, then electrical connection reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
A joining member made of amorphous silicon is introduced as an intermediary element to connect the first and second semiconductor layers across the stacked bodies. This joining member serves as a mediator that facilitates reliable electrical connection while providing a standardized interface that simplifies manufacturing alignment and reduces precision requirements compared to direct layer-to-layer connection.
Solution Approach 2:
The joining member is formed from amorphous silicon, which has different etching characteristics compared to crystalline silicon. By changing the material parameter from crystalline to amorphous silicon, the etching process becomes more selective and controllable, improving manufacturing precision while maintaining electrical connection reliability between stacked bodies.
3Manufacturing precision
If amorphous silicon is used for joining and cover layers, then etching selection ratio is improved, but material deposition complexity increases
Solution Approach 1:
The patent changes the material parameter from crystalline silicon to amorphous silicon for the joining member and cover layers. Amorphous silicon exhibits superior etching selection ratio against common dielectric materials used in semiconductor fabrication, enabling more precise patterning and etching processes. Although amorphous silicon deposition requires specific conditions (such as PECVD), the improved etching characteristics overall simplify the manufacturing process by enabling better process control and selectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the reliable fabrication of three-dimensionally stacked memory cell transistors, ensuring consistent electrical connections and suppressing variations in connection resistance, thereby enhancing the reliability and performance of the semiconductor memory device.
Implementation Method 1
using amorphous silicon for the joining and cover layers to maintain etching selection ratios and protect memory films during manufacturing
Implementation Method 2
using amorphous silicon for the joining and cover layers to maintain etching selection ratios and protect memory films during manufacturing
Implementation Method 3
a conductive joining member and cover layers to facilitate electrical connections
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.