Amorphous Silicon TFT Array Panel Leakage Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Thin film transistor array panels in liquid crystal displays suffer from leakage currents due to light-induced electron hole pairs in amorphous silicon semiconductor layers, leading to afterimages and display stains.
Innovation Solution
A thin film transistor array panel is designed with a semiconductor layer comprising three layers of amorphous silicon with different bandgap energies, where the bandgap energy of the first layer is between those of the second and third layers, and the gate insulating layer includes multiple layers, reducing leakage current through controlled deposition and gas ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer amorphous silicon semiconductor layer is used, then the device structure is simple, but leakage current increases due to light-induced electron hole pairs
Solution Approach 1:
The semiconductor layer is divided into three distinct layers with different bandgap energies. The first layer (closest to gate insulating layer) has bandgap energy of 1.6-1.8 eV, the second layer has 1.8-2.0 eV, and the third layer has 2.0-2.2 eV. This segmentation allows each layer to contribute differently to suppressing light-induced leakage current while maintaining structural organization.
Solution Approach 2:
Each semiconductor layer is assigned a specific bandgap energy range optimized for its position and function. The lower bandgap first layer effectively suppresses leakage current near the gate insulating interface, while the higher bandgap second and third layers provide progressive suppression toward the source/drain region, creating a gradient quality distribution.
2Object-generated harmful factors
If multiple semiconductor layers with different bandgap energies are used, then leakage current is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The bandgap energy of each semiconductor layer is precisely controlled by adjusting deposition parameters during PECVD processing. By varying gas flow ratios (SiH4:H2), deposition temperature, and power density, each layer achieves its target bandgap energy range, enabling systematic control of electrical properties through parameter optimization.
Solution Approach 2:
The semiconductor structure employs a composite of three amorphous silicon layers with different hydrogen content and bonding configurations, achieved through controlled PECVD deposition. This composite structure combines the benefits of varying bandgap energies while using the same base material system, simplifying manufacturing compared to using different materials.
3Object-generated harmful factors
If the bandgap energy of the first semiconductor layer is between those of the second and third layers, then leakage current suppression is optimized, but the structural design becomes more complex
Solution Approach 1:
The bandgap energy distribution creates a dynamic gradient that adapts to different operational conditions. The intermediate bandgap of the first layer (1.6-1.8 eV) provides optimal suppression for low-energy photons, while the higher bandgap second (1.8-2.0 eV) and third layers (2.0-2.2 eV) progressively suppress higher-energy photons, creating a dynamic response spectrum.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces leakage current by approximately 70%, minimizing afterimages and improving display quality by effectively controlling the bandgap energies and defects in the semiconductor layer.
Implementation Method 1
If light is radiated on the semiconductor layer of a portion protruding over line widths of source and drain electrodes, a bond of amorphous silicon molecules in the semiconductor layer is broken by light energy to form an electron hole pair (e-h pair).
Implementation Method 2
forming a semiconductor layer on the gate insulating layer, in which in the forming of the semiconductor layer, three or more semiconductor layers having different bandgap energies from one another are formed
Data Source
AI summary
A thin film transistor array panel includes a first insulating substrate, a gate electrode positioned on the first insulating substrate, a gate insulating layer positioned on the gate electrode, a semiconductor layer positioned on the gate insulating layer, and a source electrode and a drain electrode positioned on the semiconductor layer and spaced apart from each other, in which the semiconductor layer includes three or more amorphous silicon layers having different bandgap energies from one another in order to reduce a leakage current and improve performance of a liquid crystal display.