Transistor TRIZ Cases

An all-digital floating level shifter uses stacked low-voltage CMOS to block high dV/dt false triggers in GaN DC-DC converters.

Impurity-doped silicon barrier layers control inner spacer spacing near stacked nanosheets, improving source/drain and spacer reliability.

Different gate insulator layouts in pixel and driving TFTs cut parasitic capacitance while preserving carrier mobility and display reliability.

A stacked capacitor electrode above a double-gate TFT saves subpixel area while improving channel field control and current stability.

Additional capacitors stacked in parallel with the storage capacitor help high-resolution OLED pixels retain anode voltage for one frame.

By forming n-type source/drain epitaxy before p-type, this case reduces selective-loss defects on dielectric fins and eases defect removal.

A damage implant raises cap-layer etch rate after anneal, preserving stress transfer that boosts transistor drive current without more leakage.

Metal layers split one oxide TFT into multiple channel regions, adding pixel redundancy without enlarging transistor area or reducing luminance.

Ion implantation creates impurity-rich upper gate mask regions that improve contact etch selectivity and reduce leakage in scaled transistors.

Closed-loop feedback and a discharge capacitor clamp MOSFET turn-off voltage spikes without high-power TVS diodes or added heat dissipation.

A backside dielectric cap isolates the GAA gate from the backside via, preventing current leakage while preserving electrical connectivity.

Dummy pixel separation contacts stabilize alignment and cut crosstalk and dark current in highly integrated image sensors.

Switchable floating diffusion links let a 3D stacked image sensor change charge-voltage conversion efficiency without increasing chip area.

Real and fake contacts give a multiplexer cell a generic layout that hides true circuit functionality from reverse engineering.

Polar sidewalls and polarization layers let fin-based FET/TFET structures cut power use while preserving density, stability, and drive voltage.

Diffused metal seeds guide ferroelectric crystallization to control grain phase and support lower-voltage transistor switching in dense semiconductor layouts.

A recessed power rail and sidewall-contacted source contact cut resistance and parasitic capacitance while easing IC scaling constraints.

Insulating layers formed between adjacent FinFET gates block residual conductive bridging during etching, improving electrical isolation and yield.

A graded SiGe fin etches faster at the bottom than the top, creating rectangular channel profiles that improve gate control and reduce DIBL.

A dielectric structure formed in source/drain trenches blocks substrate leakage paths, suppresses DIBL, and preserves Ion/Ioff as FETs scale.

Thermal diffusion drives patterned p-type dipoles into nanosheet gate dielectrics, enabling multiple threshold voltages despite tight process windows.

Selective Al-based and Al-free work function layers with Si capping enable ultra-low threshold GAA MOSFETs with thinner gate stacks.

Different isolation widths and gate lengths let FinFET high-voltage and core devices share one substrate while reducing ADC noise and error.

A low-temperature liner layer protects spacer structures during backside contact etching, reducing shorts, leakage current, and contact resistance.

Insulating dummy fins anchor unsupported dummy gate stacks, preventing collapse and source/drain bridging in fine-pitch semiconductor fabrication.

A two-stage epitaxial source/drain with lower then higher doping cuts band-to-band tunneling and punch-through leakage in scaled nano-FETs.

Different n-type and p-type source/drain profiles cut p-type fin bending and lower contact resistance through tailored epitaxy and V-shaped contacts.

Sidewall channel structures and voltage modulation layers align threshold voltage across nonplanar transistors, cutting noise and bitline delay.

A segmented MEOL strap uses conductive segments at different heights to add current paths, lower resistance, and limit parasitic capacitance.

A sacrificial-layer etch-back isolates mixed-Vt nanosheet gates, preventing metal gate loss while preserving Vt uniformity and cell height.

A gate-isolated backside via links front-side metal in a GAA IC, improving nanosheet control while lowering routing resistance and capacitance.

A dielectric stressor beneath the gate stack boosts GAA channel mobility and lowers parasitic capacitance without adding unreliable scaling complexity.

Stacked channels with upper and lower wiring vias improve gate control, integration density, and logic circuit reliability in compact FET layouts.

A floating N-type well and STI isolation cut parasitic capacitance in FDSOI RF switches, lowering insertion loss and area.

Different gate oxide thicknesses across SOI and bulk regions help form precise metal gate shapes while improving semiconductor speed and reliability.

A through via insulating layer acts as an etch stop to prevent over-etching and secure reliable via connection to the lower wiring layer.

Monolithic 3D integration of GaN and Si CMOS addresses power delivery and RF limits with drain field plates and compact high-efficiency IC stacking.

Bismuth deposited in vertical transistor channels is annealed into a semiconductor phase, boosting carrier mobility and current speed.

ALD-formed zirconium oxide with aluminum doping cuts leakage and defects while maintaining high-k performance in display TFT dielectric layers.

A single high-pressure oxygen anneal crystallizes the ferroelectric gate layer and stabilizes channel oxygen vacancies to improve transistor performance.

Variable inner spacer widths and controlled etching cut gate-to-epitaxial capacitance in nanosheet transistors while preserving gate control.

A doped silicon interlayer and germanium JFET reduce leakage current and raise optical fill factor in image sensors.

An oscillating aluminum profile in a nitride HEMT buffer layer relaxes stress, limits wafer curvature, and prevents cracks or voids during growth.

A dielectric placeholder guides backside contact placement in nanoribbon transistors, improving alignment and integration in complex IC fabrication.

Separate transmission control line groups let image sensors adjust phase focus density without changing pixel structure or optical performance.

A dielectric-separated source/drain layout cuts direct substrate contact in GAA transistors, reducing DIBL and residual leakage.

Polarized junctions with different crystal orientations enable monolithic HEMT and HHMT integration while avoiding difficult P-type channel doping.

Si regrowth over an insulator enables on-chip PMOS with III-N NMOS, cutting multi-chip I/O complexity, RF losses, and packaging cost.

A shared n-well bias scheme lets PMOS level shifters use the higher supply voltage to prevent latch-up and save IC area.