GaN Screen Layer Integration for 2DEG Depletion Shielding

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Solution Overview

Problem

Microelectronic devices with gallium nitride components experience performance degradation due to depletion of mobile charge layers caused by potential differences between semiconductor substrates and gallium nitride components.

Innovation Solution

Incorporating a screen layer with free charge carriers over a lower buffer layer in microelectronic devices, electrically connected to a field effect transistor, which shields the two-dimensional electron gas layer from substrate potentials, reducing depletion and improving on-state resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If gallium nitride components are operated at potentials significantly above substrate potentials, then the driving voltage and power output are improved, but the mobile charge layers are depleted by potential differences, reducing component performance

Engineering Contradiction:
Improvepower outputVSAvoidcomponent performance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

A screen layer with high carrier concentration is introduced as an intermediary between the substrate and the two-dimensional electron gas layer. This screen layer acts as a mediator that shields the 2DEG from the substrate potential, allowing the device to operate at high potentials while maintaining charge layer integrity and performance

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the two-dimensional electron gas layer is shielded from substrate potential, then depletion is reduced and on-state resistance is improved, but an additional screen layer is introduced

Engineering Contradiction:
Improveon-state resistanceVSAvoidlayer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The screen layer serves multiple functions simultaneously: it provides potential shielding to protect the 2DEG from substrate effects, acts as an additional conduction path that reduces on-state resistance, and maintains device performance at high operating potentials. This multi-functionality justifies the additional layer structure

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The screen layer effectively reduces the depletion of the two-dimensional electron gas layer, thereby enhancing the on-state resistance of the field effect transistor and improving device performance.

Implementation Method 1

The screen layer is electrically connected to a current node, that is, a source node or a drain node, of the field effect transistor. During operation of the microelectronic device, the screen layer may shield the 2DEG layer from a potential on the silicon substrate, thereby reducing depletion of the 2DEG layer

Methodology Applied
Scientific EffectElectrostatic shielding: Faraday Cage

Data Source

PatentUS20240204055A1Screen layer integration in gallium nitride technology
Publication Date: 2024.06.20 TEXAS INSTRUMENTS INC
  • US20240204055A1 patent drawing
  • US20240204055A1 patent drawing
  • US20240204055A1 patent drawing

AI summary

A microelectronic device includes a lower buffer layer of III-N semiconductor material formed over a silicon substrate. A screen layer having free charge carriers is formed over the lower buffer layer. The microelectronic device may include an upper buffer layer of III-N semiconductor material formed over the screen layer. A gallium nitride field effect transistor (GaN FET) is formed over the screen layer. The GaN FET has a two-dimensional electron gas (2DEG) layer directly over at least a portion of the screen layer. The screen layer may include a doped layer of III-N semiconductor material, or a buried barrier layer with 2DEG layers in the lower and upper buffer layers. The screen layer is electrically connected to a current node, that is, a source node or a drain node, of the GaN FET.