Sacrificial Cap Layer Damage Implant for Stress-Enhanced Transistors
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Solution Overview
Problem
The existing semiconductor transistor fabrication processes face challenges in effectively transferring stress to the channel region during the source/drain anneal process, which affects carrier mobility and transistor performance, and also struggle with the removal of the sacrificial cap layer due to its densified structure post-anneal.
Innovation Solution
A sacrificial conformal cap layer, preferably SiN, is used during the source/drain anneal process to impart stress to the gate electrode, and a damage implant process is employed to increase the etch rate of the cap layer, allowing for its efficient removal without compromising transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sacrificial cap layer is used during source/drain anneal to transfer stress to the channel region, then carrier mobility and transistor drive current are improved, but the cap layer becomes densified and difficult to remove
Solution Approach 1:
The patent applies damage implantation to change the physical and chemical parameters of the cap layer by introducing defects and altering its structure. This parameter change increases the etch rate of the cap layer, making it easier to remove while maintaining the stress transfer function during annealing.
Solution Approach 2:
The damage implantation is performed as a preliminary action before the cap layer removal step. By pre-damaging the cap layer structure, the subsequent etching process becomes more effective, resolving the contradiction between maintaining cap layer integrity for stress transfer and enabling easy removal afterward.
2Duration of action of moving object
If the cap layer is maintained intact during source/drain anneal, then stress transfer to the channel is effective, but the removal process becomes time-consuming and complex
Solution Approach 1:
Damage implantation is performed as a preliminary treatment to the cap layer before removal. This pre-treatment creates structural defects that accelerate the etching process, significantly reducing the time required for cap layer removal while maintaining the integrity needed for effective stress transfer during annealing.
Solution Approach 2:
By changing the physical parameters of the cap layer through damage implantation (introducing defects, altering density), the etch rate is dramatically increased. This parameter change resolves the time contradiction by making removal faster without compromising the stress transfer function during the anneal process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cap layer effectively enhances transistor drive current by improving carrier mobility without increasing leakage current, and the damage implant ensures easy and thorough removal, maintaining process efficiency.
Implementation Method 1
A sacrificial conformal cap layer, preferably SiN, is used during the source/drain anneal process to impart stress to the gate electrode
Implementation Method 2
a damage implant process is employed to increase the etch rate of the cap layer
Data Source
AI summary
A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.