Oxide TFT Display Layout for Low Parasitic Capacitance
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Solution Overview
Problem
Display devices face challenges in minimizing parasitic capacitance in pixel transistors, which affects image quality, and in enhancing carrier mobility in driving circuit transistors to improve output characteristics.
Innovation Solution
The design includes transistors with different structures in display and non-display areas, where pixel transistors have a gate insulating layer covering the active layer to reduce parasitic capacitance, and driving circuit transistors have an etched gate insulating layer to increase carrier mobility, both using oxide semiconductors for efficient manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate insulating layer covers the entire active layer in pixel transistors, then parasitic capacitance is reduced, but carrier mobility is decreased
Solution Approach 1:
The patent applies different gate insulating layer configurations to different transistor types: pixel transistors have a gate insulating layer covering the entire active layer to minimize parasitic capacitance and improve image quality, while driving circuit transistors have an etched gate insulating layer to maximize carrier mobility and output characteristics. This local differentiation resolves the contradiction by optimizing each transistor type for its specific functional requirements.
2Reliability
If the gate insulating layer is etched to expose source and drain regions, then carrier mobility is increased, but parasitic capacitance increases
Solution Approach 1:
The patent implements location-specific gate insulating layer structures: driving circuit transistors in the non-display area have etched gate insulating layers to enhance carrier mobility for high-performance signal processing, while pixel transistors in the display area maintain covered gate insulating layers to minimize parasitic capacitance for high-quality image display. This spatial differentiation resolves the contradiction between mobility enhancement and capacitance control.
3Reliability
If different transistor structures are used in display and non-display areas, then performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent divides the substrate into display area and non-display area, and further segments the transistor population into pixel transistors and driving circuit transistors. Each segment receives a customized gate insulating layer configuration appropriate to its functional requirements. This segmentation approach enables performance optimization for each transistor type while maintaining a manageable manufacturing process through systematic differentiation.
Data Source
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AI summary
A display device includes a pixel including a first transistor, and a driving circuit including a second transistor. The first transistor includes a first active layer including first source and drain regions apart from each other with a first channel region therebetween, a first gate insulating layer on the first active layer and covering the first channel, source and drain regions, and a first gate electrode on the first gate insulating layer and overlapping the first channel region. The second transistor includes a second active layer including second source and drain regions apart from each other with a second channel region therebetween, a second gate insulating layer on a part of the second active layer including the second channel region and exposing the second source and drain regions, and a second gate electrode disposed on the second gate insulating layer and overlapping the second channel region.