MOSFET Sub-Active Pattern Isolation for Short-Channel Control
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Solution Overview
Problem
As semiconductor devices are scaled down, issues such as the short channel effect arise, leading to deteriorated operating characteristics, and there is a need for improved integration density and performance while minimizing manufacturing costs.
Innovation Solution
A semiconductor device with a simplified structure is manufactured using a device isolation layer with diffusion break regions and isolation structures, where sacrificial patterns are formed and replaced with gate electrodes, and fin spacers are used to create a gap region filled with an isolation pattern, allowing for effective isolation between sub-active patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to increase integration density, then integration density is improved, but operating characteristics deteriorate due to short channel effect
Solution Approach 1:
The active pattern is divided into multiple sub-active patterns (first sub-active pattern, second sub-active pattern, etc.) that are spaced apart from each other. This segmentation allows for better control of current flow and reduces the short channel effect while maintaining high integration density through compact arrangement of multiple sub-patterns.
Solution Approach 2:
Different regions of the device are given different properties: diffusion break regions are formed in the device isolation layer at specific locations between sub-active patterns to control carrier diffusion locally, while isolation structures are provided at other locations to provide electrical isolation. This local differentiation allows optimization of operating characteristics without compromising overall integration density.
2Reliability
If complex isolation structures are used to address short channel effect, then operating characteristics are improved, but device complexity increases
Solution Approach 1:
Multiple functions are merged into unified structures: the device isolation layer serves both as an isolation medium and as a substrate for forming diffusion break regions and isolation structures. The fin spacers serve dual purposes as both spacers during fabrication and as part of the final device structure for electrical isolation. This merging reduces the number of separate components and simplifies the overall device structure.
Solution Approach 2:
The fin spacers are designed to perform multiple functions: they act as spacers during the fabrication process to define gaps, serve as isolation structures to provide electrical isolation between sub-active patterns, and can be integrated with the gate electrode structure. This multi-functionality reduces the need for additional dedicated isolation components, thereby simplifying the device structure.
3Reliability
If advanced manufacturing processes are used to improve device performance, then operating characteristics are improved, but manufacturing cost increases
Solution Approach 1:
The device isolation layer is formed beforehand with pre-positioned diffusion break regions before the sub-active patterns are fully defined. The fin spacers are formed early in the fabrication process to establish gap regions that guide subsequent isolation structure formation. These preliminary actions simplify later manufacturing steps and reduce the need for complex alignment processes, thereby lowering manufacturing costs.
Solution Approach 2:
The fin spacers automatically define the gap regions between sub-active patterns through their physical presence during fabrication, eliminating the need for separate patterning steps to create these gaps. The isolation structures self-align to the fin spacers and sub-active patterns, reducing the need for complex alignment procedures and reducing manufacturing complexity and cost.
Data Source
AI summary
A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.