GAA Nanosheet Transistor Structure for Lower Power Dissipation
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced integrated circuits due to increased complexity and power dissipation issues as devices scale down, requiring innovative processing and materials to maintain efficiency and reduce power consumption.
Innovation Solution
The development of gate-all-around (GAA) transistor structures with epitaxial stacks and multi-gate devices, utilizing alternating semiconductor layers and dielectric walls to form nanosheet channels and high-k/metal gate structures, which allow for precise control of channel materials and gate geometry to reduce power dissipation and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency increases and costs decrease, but power dissipation increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures with vertical channels. This dimensional change increases the effective channel area and gate control without increasing the lateral footprint, thereby maintaining high functional density while improving power efficiency through better electrostatic control of the channel.
Solution Approach 2:
The patent employs selective doping regions with different dopant concentrations in specific areas of the transistor structure. By optimizing the local electrical properties in the channel and source/drain regions, the device achieves lower power dissipation while maintaining high functionality in the critical switching regions.
2Length of moving object
If scaling down process is used to increase functional density, then geometry size decreases, but processing and manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor fabrication into multiple discrete stages including separate formation of sacrificial structures, spacer deposition, and selective etching steps. This segmentation of the manufacturing process enables precise control over the final FinFET geometry while managing the complexity of creating three-dimensional structures at scaled dimensions.
Solution Approach 2:
The patent uses sacrificial structures and spacers that are formed in advance before the final channel definition. These preliminary structures guide subsequent processing steps and enable self-aligned fabrication, reducing the need for multiple alignment operations and simplifying the overall manufacturing process despite the complex final geometry.
3Loss of energy
If multi-gate devices with nanosheet channels are used, then power dissipation is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements gate structures that completely surround the nanosheet channel in a nested configuration, with the gate wrapped around all four sides of the channel. This nested gate-all-around structure provides maximum electrostatic control and minimizes power dissipation by ensuring the gate potential is applied uniformly from all directions, while the self-aligned fabrication process manages the manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of efficient, high-density semiconductor devices with reduced power consumption and improved mobility, allowing for the continued scaling of integrated circuits while maintaining performance and reducing well leakage.
Implementation Method 1
an epitaxial stack including a first plurality of epitaxial layers (128) and a second plurality of epitaxial layers (126) alternately arranged
Implementation Method 2
during the fabrication process, germanium atoms in the SiGe epitaxial layers diffuse into the Si epitaxial layers
Implementation Method 3
A first selective etching process is performed to remove the dummy gate structures (160) and the sacrificial epitaxial layers (126)
Data Source
AI summary
A method includes depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers.