Ferroelectric Gate Stack Crystallization by High-Pressure Oxygen Annealing

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Solution Overview

Problem

Current semiconductor manufacturing processes face challenges in efficiently transforming amorphous ferroelectric gate dielectric layers into crystalline ferroelectric layers with high ferroelectric phase content, which affects the ferroelectric response and doping levels in semiconductor devices, requiring multiple treatments and complex processes.

Innovation Solution

A high-pressure annealing (HPA) treatment in an oxygen environment is used to transform amorphous ferroelectric gate dielectric layers into crystalline ferroelectric layers with a high ferroelectric phase content, achieving good ferroelectric properties and stabilizing oxygen vacancies in the semiconductor channel layer, thereby improving the performance of ferroelectric transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple treatments are used to transform amorphous ferroelectric gate dielectric layers into crystalline ferroelectric layers, then the ferroelectric phase content is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improveferroelectric phase contentVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple treatment steps (crystallization annealing and oxygen treatment) into a single high-pressure annealing process performed in an oxygen environment. This single process simultaneously achieves crystallization of the ferroelectric layer and stabilization of oxygen vacancies, eliminating the need for separate treatment steps while maintaining high ferroelectric phase content

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs high-pressure annealing with specific pressure parameters (e.g., 1-10 atm) and temperature parameters (e.g., 200-400°C) to achieve phase transformation and oxygen vacancy stabilization. By optimizing these physical parameters, the process achieves high ferroelectric phase content in a single treatment step rather than requiring multiple conventional treatments

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple treatments are used to transform amorphous ferroelectric gate dielectric layers, then the ferroelectric response is improved, but the production time increases

Engineering Contradiction:
Improveferroelectric responseVSAvoidproduction time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges multiple sequential treatment processes into a single high-pressure annealing step performed in an oxygen environment. This consolidation achieves both crystallization and oxygen vacancy stabilization simultaneously, reducing the total process time while maintaining high ferroelectric response characteristics

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The high-pressure annealing process in oxygen environment continuously performs multiple functions (crystallization, phase transformation, oxygen vacancy stabilization) in an uninterrupted single step. This continuous process eliminates idle time between treatments and achieves high ferroelectric response more efficiently

Inventive Principle:
Principle #20Continuity of useful action

3Ease of manufacture

If conventional annealing processes are used, then the process is simple, but the oxygen vacancies in the semiconductor channel layer are not stabilized

Engineering Contradiction:
Improveprocess simplicityVSAvoidoxygen vacancy stabilization
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces high pressure (1-10 atm) as a key parameter modification to the conventional annealing process. This pressure parameter change enables simultaneous oxygen vacancy stabilization and crystallization in a single step, maintaining process simplicity while achieving the desired reliability outcome

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses an oxygen environment during high-pressure annealing to facilitate oxygen vacancy stabilization. The oxygen atmosphere acts as a source that fills and stabilizes oxygen vacancies in the semiconductor channel layer during the annealing process, achieving reliable oxygen vacancy stabilization without complex additional treatments

Inventive Principle:
Principle #38Strong oxidants (Accelerated oxidation)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This single pressurized treatment enhances the ferroelectric response and stability of the semiconductor channel layer, setting the threshold voltage effectively and improving the overall performance of semiconductor devices, while simplifying the fabrication process and increasing production yield.

Implementation Method 1

A pressurized treatment is performed to transform the semiconductor layer into a low-doping semiconductor layer and transform the dielectric layer into a crystalline ferroelectric layer

Methodology Applied
Scientific EffectPhase transformation: Phase Change

Implementation Method 2

A high-pressure annealing (HPA) treatment in an oxygen environment is used to transform amorphous ferroelectric gate dielectric layers into crystalline ferroelectric layers with a high ferroelectric phase content, achieving good ferroelectric properties and stabilizing oxygen vacancies in the semiconductor channel layer

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS12148828B2Semiconductor device and manufacturing method thereof
Publication Date: 2024.11.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12148828B2 patent drawing
  • US12148828B2 patent drawing
  • US12148828B2 patent drawing

AI summary

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.