3D Semiconductor Memory Stack With Gate Links Between Vertical Insulators
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the high cost and limitations of forming fine patterns, necessitating the development of three-dimensional semiconductor memory devices with improved electrical characteristics and reliability.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure comprising vertically stacked layers, including semiconductor patterns, gate electrodes, and vertical insulators, where the gate electrodes are connected through a connection portion between adjacent vertical insulators, and bit lines are electrically connected to the semiconductor patterns, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor devices are used to achieve high integration density, then manufacturing costs increase due to the need for extremely high-priced apparatuses to form fine patterns, but integration density continues to increase with limitations
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory devices. This dimensional change allows integration density to increase without requiring extremely fine pattern formation, thereby avoiding the need for extremely high-priced manufacturing apparatuses while achieving higher integration density
2Manufacturing precision
If three-dimensional vertically stacked memory devices are formed to overcome two-dimensional limitations, then integration density improves, but electrical characteristics and reliability need improvement
Solution Approach 1:
The patent divides the gate electrode into multiple segments along the vertical direction, with each segment corresponding to a specific memory cell layer. This segmentation allows independent control of each memory cell, improving electrical characteristics and reliability while maintaining high integration density through the three-dimensional stacked structure
Solution Approach 2:
The patent applies different materials and structures to different regions of the three-dimensional device. Specifically, different gate electrode materials or structures are used in different vertical segments to optimize electrical characteristics for specific memory cell layers, thereby improving overall device reliability
Data Source
AI summary
A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.