Shared-Transistor Pixel Layout for Faster Low-Noise Image Sensors
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Solution Overview
Problem
Existing image sensors face challenges in optimizing the arrangement and sharing of transistors within the pixel area to enhance signal transfer speed and reduce dark current or noise, particularly due to the limitations of transistor area configuration and isolation methods.
Innovation Solution
The image sensor design includes a transistor set with a specific arrangement of reset, source follower, and selection transistors, where transistors share common source or drain areas, and are connected in parallel to increase channel width, thereby improving transconductance and reducing RC delay, while eliminating the need for separate isolation areas to minimize dark current and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are arranged in a conventional layout, then the photodiode area is reduced, but the transconductance and signal transfer speed deteriorate
Solution Approach 1:
Adjacent transistors share common source and drain areas, merging previously separate regions into shared structures. This reduces the total transistor area while maintaining electrical functionality, thereby increasing photodiode area without compromising signal transfer speed
Solution Approach 2:
Shared source and drain areas serve multiple transistors simultaneously, making these regions multi-functional. A single source/drain area replaces what would traditionally require separate regions for each transistor, reducing overall area consumption
2Area of moving object
If transistors are arranged in a conventional layout, then the photodiode area is reduced, but the transconductance deteriorates
Solution Approach 1:
By merging source and drain areas between adjacent transistors, the patent reduces total area while maintaining the electrical pathways needed for transconductance. The shared regions preserve the necessary current flow paths
Solution Approach 2:
The patent applies different configurations to different transistor regions. Specifically, the shared source/drain areas are positioned and dimensioned to optimize transconductance for each transistor while minimizing overall area, allowing each local region to serve its specific function efficiently
3Speed
If RC delay is reduced through transistor optimization, then signal transfer speed improves, but device complexity increases
Solution Approach 1:
The patent merges source and drain areas to reduce RC delay by minimizing resistance and capacitance in the signal path. While this creates a complex-looking layout, the complexity is purely geometric rather than functional - the electrical connections remain straightforward
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances signal transfer speed and reduces noise by improving transconductance and eliminating the need for separate isolation areas, leading to more efficient image sensing.
Implementation Method 1
The pixel area may include a photodiode
Data Source
AI summary
An image sensor for securing an area of a photodiode includes a pixel area and a transistor area adjacent to the pixel area. The pixel area may include a photodiode and a floating diffusion area. The transistor area may include transistors extending along an edge of the pixel area. The transistors in the transistor area may include a reset transistor, one or more source follower transistors, and one or more selection transistors, and the reset transistor and one source follower transistor adjacent to the reset transistor may share a common drain area. The source follower transistors and the selection transistors may each share a common source area or a common drain area between two adjacent transistors thereof.