ESD Protection Structure With Isolation Layout for Lower Trigger Voltage

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Solution Overview

Problem

Electrostatic discharge (ESD) can cause damage to integrated circuits due to transient power discharge when charged bodies come into contact with chips or wafers, and existing ESD protection structures are inadequate in managing this issue effectively.

Innovation Solution

An ESD protection structure is designed with a semiconductor substrate, including a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure, where the isolation structure is positioned between the first and second p-type doped regions, and the distance between the first p-type doped region and the edge of the n-type well region is controlled to improve operation characteristics, such as lowering trigger and breakdown voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the isolation structure is placed between the first p-type doped region and the second p-type doped region with controlled distance, then the ESD protection efficiency is improved through punch-through breakdown, but the device complexity increases due to precise positioning requirements

Engineering Contradiction:
ImproveESD protection efficiencyVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure serves as an intermediary element positioned between the first p-type doped region and the second p-type doped region. This intermediate structure enables controlled punch-through breakdown while providing electrical isolation, thus improving ESD protection efficiency without requiring direct contact between the doped regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent controls the distance parameter between the first p-type doped region and the isolation structure edge to optimize punch-through breakdown characteristics. By adjusting this dimensional parameter, the trigger voltage and breakdown voltage are lowered, improving ESD protection while maintaining a relatively simple structure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the distance between the first p-type doped region and the edge of the n-type well region is reduced, then the trigger voltage and breakdown voltage are lowered for better ESD protection, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvetrigger voltage controlVSAvoiddistance control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent optimizes the distance parameter between the first p-type doped region and the n-type well region edge to achieve desired trigger voltage and breakdown voltage characteristics. By carefully controlling this dimensional parameter, the structure enables lower voltages for ESD protection while maintaining manufacturability through standard fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The controlled distance and placement of the isolation structure enhance the ESD protection efficiency by facilitating punch-through breakdown, thereby improving the protection of integrated circuits from electrostatic discharge.

Implementation Method 1

The controlled distance and placement of the isolation structure enhance the ESD protection efficiency by facilitating punch-through breakdown

Methodology Applied
Scientific EffectPunch-through breakdown: Avalanche Breakdown

Data Source

PatentUS20240194668A1Electrostatic discharge protection structure
Publication Date: 2024.06.13 UNITED MICROELECTRONICS CORP
  • US20240194668A1 patent drawing
  • US20240194668A1 patent drawing
  • US20240194668A1 patent drawing

AI summary

An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.