Ferroelectric Gate Structure for Scaled MOSFET Voltage Reduction
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate, and existing methods struggle to maintain superior performance and integration while addressing issues related to high integration and scaling.
Innovation Solution
The integration of a ferroelectric pattern between semiconductor patterns and a gate electrode, which includes a work function metal pattern, to enhance electrical characteristics by producing a negative capacitance effect, improving sub-threshold swing characteristics and reducing operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to maintain high integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent introduces a ferroelectric layer in the gate structure that changes the electrical parameters of the transistor by producing negative capacitance effect, thereby improving sub-threshold swing characteristics and reducing operating voltage without changing the physical scale of the device
Solution Approach 2:
The gate electrode is constructed as a composite structure including a ferroelectric layer combined with work function metal patterns, creating a multi-material system that leverages the unique properties of each material to achieve both high integration and superior operating characteristics
2Ease of manufacture
If conventional gate structures are used in scaled devices, then manufacturing is simpler, but sub-threshold swing characteristics are insufficient
Solution Approach 1:
The gate electrode is divided into multiple functional segments including a ferroelectric layer and work function metal patterns, where each segment performs a specific function that collectively improves sub-threshold swing characteristics while maintaining manufacturing feasibility through standardized fabrication processes
3Device complexity
If standard gate electrode configurations are used, then device structure is simpler, but operating voltage remains high
Solution Approach 1:
The ferroelectric layer fundamentally changes the electrical parameters of the gate structure by introducing negative capacitance, which amplifies the gate voltage effect and enables lower operating voltages without requiring complex external circuitry or additional device layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves sub-threshold swing characteristics and reduces operating voltage, enhancing the overall performance of semiconductor devices by leveraging the negative capacitance effect caused by the ferroelectric pattern.
Implementation Method 1
The integration of a ferroelectric pattern between semiconductor patterns and a gate electrode, which includes a work function metal pattern, to enhance electrical characteristics by producing a negative capacitance effect
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.