Switching Field Plate Power MOSFET for Breakdown Voltage Trade-off
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Solution Overview
Problem
Current power MOSFET technologies face challenges in achieving optimal trade-offs between breakdown voltage and on-state resistance, leading to inefficiencies in power density and heat management in power electronics applications.
Innovation Solution
The integration of a source-down enhancement mode transistor and a depletion mode transistor with a switchably connectable field plate in a semiconductor substrate, along with control circuitry to manage the field plate's state, allows for improved breakdown voltage and reduced on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the breakdown voltage is increased in the MOSFET design, then the device can handle higher power levels, but the on-state resistance increases leading to higher conduction losses
Solution Approach 1:
The patent segments the channel into two distinct regions: an enhancement mode transistor channel and a depletion mode transistor channel. These segments are connected in series, allowing each segment to be optimized independently for its specific function, thereby resolving the trade-off between breakdown voltage and conduction losses
Solution Approach 2:
Different regions of the device are assigned different doping characteristics: the enhancement mode region has heavier doping for low on-resistance, while the depletion mode region has lighter doping for high breakdown voltage. This local differentiation allows each region to perform its specialized function optimally
2Loss of energy
If the on-state resistance is reduced to improve efficiency, then conduction losses decrease, but the breakdown voltage capability is compromised
Solution Approach 1:
The patent divides the transistor into two functional segments connected in series: an enhancement mode transistor for low on-resistance operation and a depletion mode transistor for high breakdown voltage capability. This segmentation allows simultaneous optimization of both parameters
Solution Approach 2:
The patent changes the doping parameters along the channel length, transitioning from heavier doping in the enhancement mode region to lighter doping in the depletion mode region. This parameter gradient enables the device to achieve both low conduction losses and high breakdown voltage
Data Source
AI summary
A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.