Epitaxial Source/Drain SiGe Stack for Dopant Diffusion Control

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area, including issues with dopant diffusion and the short channel effect, which affect device performance and integration density.

Innovation Solution

The formation of epitaxial source/drain regions using a bottom layer of silicon-germanium doped with arsenic, which increases activated dopant concentration and blocks other dopants from diffusing, thereby improving device performance and integration density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but dopant diffusion and reduced solid solubility of dopants occur affecting device performance and reliability

Engineering Contradiction:
Improveintegration densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material composition parameter by incorporating silicon-germanium (SiGe) instead of pure silicon, and adjusts the germanium concentration parameter (e.g., 5-20% Ge) to optimize both integration density and dopant solid solubility, thereby resolving the contradiction between scaling and device performance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite silicon-germanium materials combining silicon and germanium in specific ratios to create source/drain regions with enhanced properties, where the composite structure provides both the scaling benefits and the improved dopant retention needed to maintain reliability

Inventive Principle:
Principle #40Composite materials

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but dopant diffusion increases affecting device performance

Engineering Contradiction:
Improveintegration densityVSAvoiddopant diffusion
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary silicon-germanium layer between the dopant source and the channel region, where the specific Ge concentration acts as a mediator to control and reduce unwanted dopant diffusion while allowing necessary dopant incorporation for device operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By changing the germanium concentration parameter in the SiGe alloy, the patent optimizes the balance between allowing sufficient dopant incorporation for functionality and preventing excessive dopant diffusion that would harm device performance

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the integration density of semiconductor devices by increasing the concentration of activated dopants and reducing dopant diffusion, thereby improving device performance and addressing the short channel effect.

Implementation Method 1

silicon-germanium (SiGe) doped with arsenic (As) to enhance dopant concentration and block diffusion

Methodology Applied
Scientific EffectSolid solution strengthening: Solid Solution Strengthening

Implementation Method 2

block diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 3

multi-layer epitaxial structure to improve solid solubility and control stress

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240186415A1Semiconductor Device and Methods of Forming Same
Publication Date: 2024.06.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240186415A1 patent drawing
  • US20240186415A1 patent drawing
  • US20240186415A1 patent drawing

AI summary

A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.