Stacked MOSFET Channel Support Structure for Bending Stability
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to challenges in achieving improved electrical performance and structural stability due to increased integration and channel length variations.
Innovation Solution
The semiconductor device incorporates a support pattern between vertically adjacent semiconductor patterns, connecting them mechanically and electrically, with a specific ratio of support pattern width to channel length, and includes impurities like helium, to maintain structural integrity and enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density is improved, but operating characteristics and electrical performance deteriorate
Solution Approach 1:
The patent introduces vertically stacked semiconductor patterns (first, second, and third semiconductor patterns stacked in the vertical direction) to form multi-bridge channels. This three-dimensional structure increases the effective channel width without increasing the planar footprint, thereby improving device density while maintaining adequate channel length for proper electrical characteristics.
Solution Approach 2:
The patent introduces support patterns positioned between vertically adjacent semiconductor patterns as intermediary structures. These support patterns provide mechanical stabilization to prevent channel bending and maintain structural integrity of the stacked configuration, thereby preserving electrical performance while enabling the vertical stacking for higher density.
2Reliability
If channel length is increased to improve electrical characteristics, then operating performance is improved, but structural stability deteriorates due to channel bending
Solution Approach 1:
The support patterns act as intermediary structures positioned between vertically adjacent semiconductor patterns. These support patterns provide mechanical reinforcement that stabilizes the long channel structure, preventing bending while maintaining the required channel length for good electrical characteristics.
Solution Approach 2:
The patent creates a composite structure by integrating support patterns with the semiconductor patterns. The support patterns (which may have different material properties, such as containing helium impurities) are combined with the semiconductor patterns to form a composite structure that provides both the necessary electrical characteristics and structural stability.
3Productivity
If vertically stacked semiconductor patterns are formed to increase effective channel width, then device density is improved, but structural integrity deteriorates due to channel bending
Solution Approach 1:
The support patterns serve as intermediary structures positioned between vertically adjacent semiconductor patterns. These support patterns provide mechanical reinforcement that prevents bending of the stacked semiconductor patterns, thereby maintaining structural integrity while enabling the vertical stacking configuration for improved device density.
4Stability of the object's composition
If support pattern width is increased to prevent channel bending, then structural stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies that the support pattern width is controlled within a particular range (about 0.05 to 0.2 times the channel length). This parameter optimization provides sufficient structural support to prevent channel bending while maintaining manufacturability with standard fabrication tolerances, avoiding excessive precision requirements.
Data Source
AI summary
Disclosed are semiconductor devices and/or method of fabricating the same. The semiconductor device comprises a substrate including first and second regions, a first active pattern on the first region and including a pair of first source/drain patterns and a first channel pattern including first semiconductor patterns, a second active pattern on the second region and including a pair of second source/drain patterns and a second channel pattern including second semiconductor patterns, a support pattern between two vertically adjacent first semiconductor patterns, and a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern. A channel length of the first channel pattern is greater than that of the second channel pattern. A ratio of a width of the support pattern to the channel length of the first channel pattern is in a range of 0.05 to 0.2.