Group III Nitride Complementary Circuit Using Polarized Junctions
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Solution Overview
Problem
The development of integrated circuits using group III nitride semiconductors faces challenges in achieving monolithic integration of P-channel and N-channel devices due to difficulties in P-type doping and realizing normally-off transistors with high mobility and low on-resistance, primarily because of the strong polarization effect and normally-on characteristics of two-dimensional carrier gases at heterojunction interfaces.
Innovation Solution
The proposed solution involves an integrated circuit structure with transistors having polarized junctions of different crystal orientations, utilizing two-dimensional electron and hole gases to form carrier channels, and incorporating doped regions to achieve normally-off operation, enabling complementary integration of high electron mobility transistors (HEMT) and high hole mobility transistors (HHMT) on a common substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If P-type doping is attempted in group III nitride semiconductor to create P-channel devices, then complementary integration is enabled, but doping difficulty and manufacturing complexity increase significantly
Solution Approach 1:
The patent introduces a heterojunction interface (e.g., AlGaN/GaAs or AlN/GaN) as an intermediary structure that generates two-dimensional hole gas (2DHG) without requiring direct P-type doping of the channel region. The polarization effect at the heterojunction interface serves as the mediator to create the P-channel carrier gas, bypassing the difficult P-type doping process while enabling complementary integration.
Solution Approach 2:
The patent changes the fundamental parameter of carrier generation from doping-based to polarization-based. By utilizing the strong polarization effect in group III nitride heterojunctions, the invention transforms how P-channel carriers are created, shifting from chemical doping to physical polarization-induced carrier accumulation, thereby avoiding doping-related manufacturing difficulties.
2Speed
If heterojunction structure is used to create high mobility transistor, then carrier mobility is improved, but normally-on characteristics are generated which require additional control mechanisms
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions: the heterojunction interface region that provides high mobility through polarization-induced carrier gas, and the gate control region that independently manages the normally-off characteristic. This segmentation allows the high mobility channel and the control mechanism to be optimized separately while working together.
Solution Approach 2:
The patent applies local quality by creating different properties in different regions: the heterojunction interface region maintains high carrier mobility through polarization effects, while the gate region and channel interface are engineered with specific doping profiles or barrier structures to enable normally-off operation. Each region has optimized local properties to fulfill its specific function.
3Speed
If discrete devices are used, then high switching speed is achieved, but inter-chip parasitic inductance limits performance
Solution Approach 1:
The patent merges multiple transistor devices into a single integrated circuit chip, combining P-channel and N-channel high mobility transistors on the same substrate. This integration eliminates the inter-chip connections that cause parasitic inductance, while maintaining the high switching speed benefits of the individual devices through monolithic integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the realization of high-performance, normally-off transistors with low on-resistance and high integration density, overcoming the limitations of conventional silicon-based CMOS circuits by leveraging the polarization characteristics of group III nitride semiconductors, resulting in improved carrier mobility and reduced parasitic inductance.
Implementation Method 1
Since a group III nitride semiconductor heterojunction has a strong polarization effect, high concentration of two-dimensional carrier gas exists at a heterojunction interface
Data Source
AI summary
The present disclosure provides an integrated circuit structure of a group III nitride semiconductor, a manufacturing method thereof, and use thereof. The integrated circuit structure is a complementary circuit of HEMT and HHMT based on the group III nitride semiconductor, and can realize the integration of HEMT and HHMT on the same substrate, and the HEMT and the HHMT respectively have a polarized junction with a vertical interface, the crystal orientations of the polarized junctions of the HEMT and the HHMT are different, the two-dimensional carrier gas forms a carrier channel in a direction parallel to the polarized junction, and corresponding channel carriers are almost depleted by burying the doped region.