Stacked GAA Upper Channel Removal With Protected Lower Nanoribbons
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Solution Overview
Problem
In integrated circuit technology, the challenge lies in efficiently forming stacked semiconductor devices with high transistor density while maintaining the operational integrity of lower devices without affecting the upper devices, particularly in three-dimensional integration where removing channel regions from upper devices without impacting lower devices is crucial for optimal performance.
Innovation Solution
The approach involves forming upper devices with end sections of nanoribbons wrapped by inner gate spacers, while the central sections are removed, allowing the gate structure to wrap around only the lower device's nanoribbons, and using selective etch processes to maintain the operational channel regions of lower devices without disrupting the upper device's structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If selective etch processes are used to remove channel regions from upper devices, then transistor density is improved, but risk of damaging lower device channel regions increases
Solution Approach 1:
The patent introduces an intermediary protective layer (mask or sacrificial layer) that is selectively positioned over the lower device channel regions before the etch process. This intermediary layer acts as a barrier that allows the etch chemistry to remove upper device channels while preventing damage to the lower device channels. After etching, the protective layer is removed, leaving the lower device channels intact and functional.
Solution Approach 2:
The patent applies different protective measures to different spatial locations within the stacked device structure. Specifically, protective layers or masks are applied only to regions where lower device channels are present, while leaving upper device regions exposed to the etch process. This localized protection strategy enables selective removal of upper channels without compromising lower device operational integrity.
2Productivity
If upper device channel regions are removed to create non-operational upper devices, then transistor density is enhanced, but device structural complexity increases
Solution Approach 1:
The patent extracts or removes the channel regions from upper devices while leaving other structural elements (such as source/drain regions, gate structures, and insulating layers) intact. This selective extraction creates non-operational upper devices that still maintain the physical framework necessary for stacking, thereby increasing transistor density without proportionally increasing overall structural complexity.
Solution Approach 2:
The patent designs the stacked device structure so that certain components serve multiple functions: the gate structures and source/drain regions of upper devices serve as placeholders for future operational devices while also providing structural support and electrical isolation for the lower operational devices. This multi-functionality reduces the need for additional structural elements, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of stacked semiconductor devices with enhanced transistor density by ensuring the operational continuity of lower devices while making upper devices non-operational, thereby optimizing the performance and density of integrated circuits.
Implementation Method 1
using selective etch processes to maintain the operational channel regions of lower devices without disrupting the upper device's structure
Data Source
AI summary
A semiconductor structure includes a second device stacked over a first device. In an example, the first device includes (i) a first source region, (ii) a first drain region, (iii) a body including a semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. The body can be, for instance, a nanoribbon, nanosheet, or nanowire. In an example, the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the second device lacks a continuous body extending laterally from the second source region to the second drain region.