Nanosheet Inner Spacer Layout for Lower Gate-to-Epi Capacitance
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Solution Overview
Problem
Conventional nano-sheet-based devices suffer from high capacitance between the gate electrode and epitaxial features, limiting their operational speed and performance.
Innovation Solution
The method involves forming nano-sheet-based devices with gate portions of substantially equal lengths by adjusting the etch rates of semiconductor layers with varying germanium atomic percentages, reducing the total capacitance and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nano-sheet-based devices are used, then gate control is improved and short-channel effects are reduced, but capacitance between gate electrode and epitaxial features increases
Solution Approach 1:
The gate electrode is divided into multiple gate portions, each corresponding to a specific semiconductor layer. This segmentation allows independent control of gate lengths for different layers, enabling reduction of overlapping areas between gate electrode and epitaxial features, thereby reducing capacitance while maintaining gate control.
Solution Approach 2:
Different gate portions are designed with different lengths tailored to the thickness and characteristics of individual semiconductor layers. This local optimization ensures that each gate portion provides adequate control for its corresponding layer while minimizing overall capacitance by reducing unnecessary overlapping areas.
2Reliability
If gate electrode dimensions are increased to improve gate control, then device performance is improved, but capacitance between gate electrode and epitaxial features increases
Solution Approach 1:
The gate electrode is segmented into multiple portions with different lengths, allowing each portion to be optimized for its specific function. This enables adequate gate control for each semiconductor layer thickness without requiring a uniformly large gate electrode that would increase overall capacitance.
Solution Approach 2:
The gate length parameter is varied across different gate portions to match the thickness and electrical characteristics of individual semiconductor layers. This parameter optimization achieves effective gate control while minimizing the total overlapping area and capacitance between the gate electrode and epitaxial features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall capacitance between the source/drain features and the gate electrode, leading to higher operational speeds and improved device performance.
Implementation Method 1
adjusting the etch rates of semiconductor layers with varying germanium atomic percentages
Data Source
AI summary
A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.