TiN Work-Function Deposition for FinFET Threshold Tuning
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Solution Overview
Problem
Conventional polysilicon gates in MOS devices experience poly-depletion effects, leading to increased effective gate dielectric thickness and difficulty in generating an inversion layer, which is not adequately addressed by existing metal gate technologies.
Innovation Solution
The method involves forming Fin Field-Effect Transistors (FinFETs) with work-function layers of titanium nitride, where the deposition temperature is adjusted to tune the work function, allowing for different work functions in PMOS transistors by varying the formation temperature between 300°C and 500°C, thereby adjusting the threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gates are used in MOS devices, then the gate structure is simple and easy to manufacture, but poly-depletion effects occur leading to increased effective gate dielectric thickness and difficulty in generating inversion layer
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal (such as tungsten, cobalt, or titanium nitride), fundamentally altering the electrical properties of the gate. This material substitution eliminates the poly-depletion effect by providing a metal gate with constant potential, thereby enabling effective inversion layer generation while maintaining manufacturing feasibility through established metal deposition techniques
2Reliability
If metal gates are used to eliminate poly-depletion effect, then inversion layer generation is improved, but the work function cannot be adequately tuned for different transistor types
Solution Approach 1:
The patent employs composite material structures consisting of multiple metal layers (e.g., tungsten layer combined with titanium nitride layer, or cobalt layer combined with manganese oxide layer). By combining different materials with complementary properties, the gate structure achieves both the poly-depletion elimination of metal gates and the work function tunability needed for different transistor types through controlled material composition and thickness ratios
Solution Approach 2:
The patent applies different material compositions and thicknesses to specific regions of the gate structure to achieve location-dependent work functions. By varying the local material properties (such as using different thickness ratios of metal layers in NMOS versus PMOS regions), the gate can be optimized for specific transistor types while maintaining the overall metal gate architecture
3Adaptability or versatility
If multiple metal layers are deposited to achieve different work functions for NMOS and PMOS, then work function tunability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary patterning actions by defining etch masks that selectively protect regions intended for different transistor types before the metal layer deposition. This preliminary region differentiation allows subsequent single-step metal deposition to create work function variations across different device regions, avoiding the need for multiple separate deposition processes and reducing overall manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively tunes the work functions of PMOS transistors, allowing for distinct threshold voltages and improved transistor performance by adjusting the deposition temperature of titanium nitride layers, reducing the poly-depletion effect and enhancing semiconductor device efficiency.
Implementation Method 1
depositing a first titanium nitride layer over the first gate dielectric as a work-function layer, wherein the first titanium nitride layer is deposited at a first temperature in a first range between about 300° C. and about 400° C.
Data Source
AI summary
A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.