Thin-Sheet FinFET Structure With 2D Channel for Uniform Threshold Voltage
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Solution Overview
Problem
FinFETs face performance degradation and increased resistance due to reduced fin size, leading to variations in carrier mobility and threshold voltage, making it challenging to maintain consistent performance and efficiency.
Innovation Solution
The use of a thin-sheet FinFET structure with a sheet layer, such as graphene or transition metal dichalcogenides, draped over a rib structure, which enhances carrier mobility and reduces resistance by increasing the contact area between the channel and the gate, thereby improving performance consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin size is reduced to increase device density, then device density is improved, but carrier mobility and performance consistency deteriorate due to increased resistance and threshold voltage variations
Solution Approach 1:
The patent employs a thin-sheet channel structure with thickness of 3 nm or less, which acts as a flexible thin film that maintains uniform electrical properties across the channel. This thin-sheet configuration reduces resistance variations and improves carrier mobility consistency, directly addressing the reliability issue while maintaining high device density through the scaled dimensions.
Solution Approach 2:
The patent changes the critical dimension parameter by reducing channel thickness to 3 nm or less, which fundamentally alters the electrical characteristics of the device. This parameter change enables better control over threshold voltage and carrier mobility, improving performance consistency despite the reduced fin size used to achieve high device density.
2Productivity
If fin size is reduced to increase device density, then device density is improved, but channel resistance increases leading to performance degradation
Solution Approach 1:
The thin-sheet channel structure with thickness of 3 nm or less reduces channel resistance by providing a more uniform current distribution and reducing scattering effects. This thin film approach maintains low resistance even as fin dimensions are reduced to increase device density, thereby reducing energy loss.
Solution Approach 2:
The patent utilizes composite material structures including the thin-sheet channel combined with specific gate dielectric materials and contact structures. This composite approach optimizes the overall electrical characteristics, reducing channel resistance and energy loss while maintaining the scaled dimensions necessary for high device density.
3Ease of manufacture
If conventional planar fabrication techniques are used for FinFETs, then manufacturing simplicity is maintained, but fabrication complexity increases due to non-planar structure requirements
Solution Approach 1:
The patent addresses fabrication complexity by transitioning from planar to three-dimensional FinFET structures with thin-sheet channels. This dimensional change enables better gate control and performance while the fabrication process integrates sequential deposition and etching steps that, although more complex than planar processes, follow systematic patterns that can be manufactured with appropriate tooling and process control.
Data Source
AI summary
Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.