Buried Gate Structure With Low-k Protection Layer Against GIDL
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes lead to gate-induced drain leakage (GIDL) due to consumption of the gate dielectric layer, resulting in deteriorated operational reliability and reduced data retention time.
Innovation Solution
A method involving the formation of a protection layer with a low dielectric constant between the gate electrodes, which prevents the gate dielectric layer from being damaged during the manufacturing process, thereby reducing the effective electric field and mitigating GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate dielectric layer is consumed during manufacturing, then the manufacturing process is simplified, but the effective electric field increases causing GIDL and reducing reliability
Solution Approach 1:
A protection layer is formed on the gate dielectric layer before manufacturing processes that could cause consumption or damage. This preliminary protective action prevents the gate dielectric layer from being consumed during subsequent manufacturing steps, thereby maintaining the effective electric field and preventing GIDL while ensuring manufacturing feasibility
Solution Approach 2:
The protection layer acts as an intermediary between the gate dielectric layer and the manufacturing process. It absorbs the potential damage or consumption from manufacturing operations, protecting the underlying gate dielectric layer from direct exposure to harmful processes while allowing the manufacturing to proceed
2Productivity
If the effective electric field is increased to improve device performance, then device performance improves, but GIDL occurs and data retention time decreases
Solution Approach 1:
The protection layer is applied in advance to prevent damage to the gate dielectric layer. By preserving the integrity of the gate dielectric layer, the effective electric field can be maintained at optimal levels for device performance while preventing the field enhancement that would otherwise cause GIDL and data retention loss
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a trench in a substrate and disposing a lower gate electrode in the trench. The method also includes disposing a first dielectric layer on the lower gate electrode in the trench and partially removing the first dielectric layer to expose a portion of the lower gate electrode