Vertical SOI SCR ESD Protection Seed Hole
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current Silicon on Insulator (SOI) technologies face challenges in providing effective ElectroStatic Discharge (ESD) protection for CMOS Integrated Circuits due to the difficulty in designing conventional Silicon Controlled Rectifiers (SCRs) that occupy minimal chip active area, as they require large tracts of active space and are prone to latch-up issues.
Innovation Solution
The development of vertical Silicon Controlled Rectifiers, vertical bipolar transistors, capacitors, and resistors formed through a seed hole in the SOI surface layer and substrate, utilizing buried diffusion and doped epitaxial layers, which minimizes chip real estate while providing robust ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SCR structures are used in SOI technology, then ESD protection is provided, but large chip active area is required
Solution Approach 1:
The patent transitions from planar SCR structures to vertical SCR structures by extending the device into the third dimension (depth). The vertical SCR is formed with a seed hole extending through the SOI surface layer and insulator layer to the substrate, with buried diffusion, doped epitaxial layers, and polysilicon layers stacked vertically. This vertical configuration provides equivalent ESD protection while occupying significantly less chip surface area compared to conventional planar SCR designs.
2Reliability
If conventional SCR structures are used in SOI technology, then ESD protection is provided, but device complexity increases
Solution Approach 1:
The vertical SCR structure is segmented into distinct functional layers: a seed hole region, buried diffusion layer, doped epitaxial layers with multiple doped regions, and polysilicon layers. Each segment performs a specific function in the ESD protection mechanism. This segmentation allows for optimized doping profiles and layer thicknesses that simplify the overall device operation while maintaining effective ESD protection.
Solution Approach 2:
The patent inverts the conventional SCR structure by forming the vertical configuration with the seed hole extending downward to the substrate rather than expanding laterally. The doping sequence is also inverted with buried diffusion formed first through the seed hole, followed by epitaxial growth and subsequent doping steps. This inverted approach simplifies the fabrication process by utilizing vertical stacking instead of complex lateral patterning.
3Area of stationary object
If vertical SCR structure is implemented, then chip active area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The seed hole is formed preliminarily through the SOI surface layer and insulator layer to the substrate before any doping or epitaxial growth occurs. This preliminary structuring establishes precise vertical alignment for subsequent processing steps. The buried diffusion is then formed within this pre-defined seed hole region, ensuring accurate spatial positioning. This preliminary action approach reduces the need for high-precision alignment in later doping and layer formation steps.
Solution Approach 2:
The patent uses disposable sacrificial layers and temporary structures during fabrication that are removed after serving their purpose. The seed hole structure and certain temporary doping profiles are used to guide the formation of the final vertical SCR but are not part of the final device structure. This approach allows for relaxed manufacturing precision requirements as these temporary structures can be formed with standard tolerances and then removed, leaving only the final precise vertical SCR structure.
Data Source
AI summary
A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.