Vertical 2D Transistor Assembly With Electrostatic Source-Drain Doping
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Solution Overview
Problem
The integration of two-dimensional-materials into transistors is hindered by crystalline defects that negatively impact their electrical characteristics, making it challenging to develop high-quality transistor devices with improved performance.
Innovation Solution
The use of electrostatic-doping-materials adjacent to the source/drain regions of two-dimensional-materials in vertical transistors to impart desired carrier properties, combined with the deposition of two-dimensional-materials along the sidewalls and upper surfaces of structures, forming a monocrystalline or substantially monocrystalline layer for enhanced transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two-dimensional-materials are grown in bulk amounts, then large area coverage is achieved, but crystalline defects increase
Solution Approach 1:
The patent segments the two-dimensional material deposition into localized regions along the sidewalls and upper surfaces of vertical transistor structures. Instead of attempting to grow large-area bulk material, the invention deposits material in controlled segments corresponding to specific transistor regions, thereby avoiding the crystalline defects associated with bulk growth while achieving sufficient area coverage for device fabrication
Solution Approach 2:
The patent applies local quality by depositing two-dimensional materials with different characteristics in different locations. The material is deposited along sidewalls and upper surfaces with specific orientations and properties tailored to each region's functional requirements, rather than using uniform bulk-grown material throughout. This localized deposition strategy maintains high crystalline quality in each region while achieving overall area coverage
2Reliability
If electrostatic-doping-material is added adjacent to source/drain regions, then carrier properties are improved, but device complexity increases
Solution Approach 1:
The patent merges the electrostatic doping function with the existing gate structure by positioning the electrostatic-doping-material adjacent to source/drain regions in close proximity to the gate. This integration allows the doping effect to be achieved without adding completely separate control mechanisms, thereby improving carrier properties while limiting the increase in device complexity through spatial consolidation of functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical characteristics of two-dimensional-material-based transistors by tailoring carrier behavior, reducing defects, and achieving better operability, thereby enhancing the performance of transistor devices.
Implementation Method 1
electrostatic-doping-material adjacent to source/drain regions of the active material and utilized to impart desired carrier properties to the source/drain regions
Implementation Method 2
deposition of two-dimensional-materials along the sidewalls and upper surfaces of structures, forming a monocrystalline or substantially monocrystalline layer
Data Source
AI summary
Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.