Dual-Gate Heterostructure TFT for Higher Electron Mobility
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Solution Overview
Problem
Existing thin film transistors in display panels have low electron mobility, which is a critical issue that needs to be addressed to improve device performance.
Innovation Solution
A thin film transistor structure comprising a heterostructure active layer formed by three layers - a first active layer, a second active layer, and a third active layer - with the latter two having different forbidden band widths, along with a dual-gate structure and high-K insulating layers, to enhance electron mobility by forming dual channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer active layer is used, then the device structure is simple, but the electron mobility is low
Solution Approach 1:
The active layer is divided into three distinct sub-layers (first, second, and third active layers) with different band gap widths, where the second layer has a smaller band gap than the first and third layers. This segmentation creates dual heterojunction interfaces that form two inversion layers, enabling dual-channel conduction and significantly improving electron mobility while maintaining manageable structural complexity
Solution Approach 2:
The patent employs composite material structure by combining different oxide semiconductor materials with varying band gap widths in a stacked configuration. The heterostructure comprises materials such as IGZO (indium gallium zinc oxide) and IZO (indium zinc oxide) arranged in specific sequences to create favorable energy band alignment, forming a composite active layer that leverages the advantages of each material to enhance electron transport
2Reliability
If a heterostructure with multiple active layers is used, then the electron mobility is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The manufacturing process is segmented into distinct deposition stages for forming each active layer, allowing for optimized process parameters at each stage. The first, second, and third active layers are deposited sequentially with controlled thicknesses (5-20 nm each), enabling precise control over the heterostructure formation while maintaining compatibility with existing thin-film transistor manufacturing workflows
Solution Approach 2:
The patent utilizes parameter changes in the deposition process, specifically controlling the thickness of each active layer (5-20 nm) and adjusting deposition conditions to achieve the desired band gap characteristics. By precisely controlling these parameters during manufacturing, the complex heterostructure can be formed with reproducible electron mobility enhancement
3Speed
If the active layer thickness is reduced to 5-20 nm, then the switching speed is improved, but the manufacturing precision requirement increases
Solution Approach 1:
Instead of depositing a single thick active layer, the structure is segmented into three thinner sub-layers, each 5-20 nm thick. This segmentation approach allows for better control over the total thickness and individual layer uniformity, as thinner layers are easier to deposit uniformly using standard thin-film techniques, thereby reducing the overall manufacturing precision burden while achieving faster switching speeds
Solution Approach 2:
The patent specifies a thickness range (5-20 nm) for each active layer rather than a single precise value, allowing manufacturers some flexibility in the exact thickness while still achieving the desired performance. This partial specification approach balances the need for thin layers to enable fast switching with the practical constraints of manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The heterostructure active layer configuration increases electron mobility and improves the on-state current of the device by creating dual channels, effectively addressing the low mobility issue in existing oxide semiconductive thin film transistors.
Implementation Method 1
the first active layer, the second active layer, and the third active layer form a heterostructure
Implementation Method 2
The heterostructure may form two inversion layers or depletion layers, at an interface of the first active layer and the second active layer and at an interface of the second active layer and the third active layer
Implementation Method 3
a forbidden band width of the second active layer is different from a forbidden band width of the first active layer and a forbidden band width of the third active layer
Implementation Method 4
a first gate electrode; a first insulating layer covering the first gate electrode... a second insulating layer covering the active layer, the source electrode and the drain electrode; and a second gate electrode located on the second insulating layer
Data Source
AI summary
The present disclosure provides a thin film transistor and a method of manufacturing the same, wherein the thin film transistor at least comprises a first gate electrode, a first insulating layer, an active layer, a source electrode and a drain electrode, a second insulating layer covering the active layer, the source electrode and the drain electrode, and a second gate electrode, wherein the active layer comprises a first active layer, a second active layer on the first active layer, and a third active layer on the second active layer; wherein the first active layer, the second active layer, and the third active layer may form a heterostructure.