Nanosheet Semiconductor Structure With Etch Stop Leakage Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling integration density and controlling current without increasing gate length, particularly in suppressing short channel effects and preventing etching of source/drain regions during the replacement metal gate process.
Innovation Solution
Incorporating silicon germanium (SiGe) nanosheets in PMOS regions and using insulating etch stop layers to prevent etching during the replacement metal gate process, thereby reducing leakage current and maintaining the integrity of the active patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon-based nanosheets are used in PMOS regions, then the device structure is simple, but the source/drain region is etched during the replacement metal gate process causing leakage current
Solution Approach 1:
The patent applies different material compositions to nanosheets in different device regions. Specifically, PMOS region nanosheets contain silicon germanium (SiGe) while NMOS region nanosheets contain pure silicon, allowing each region to have optimized properties for its specific function and etching resistance requirements
Solution Approach 2:
The patent uses composite silicon germanium (SiGe) material for PMOS nanosheets, combining silicon and germanium elements to create a material that provides both the desired electrical characteristics and enhanced etching resistance during the replacement metal gate process
2Reliability
If etch stop layer is added under PMOS nanosheets, then source/drain etching is prevented, but the manufacturing process becomes more complex
Solution Approach 1:
The patent incorporates an etch stop layer beneath the PMOS nanosheets before the nanosheets are formed. This preliminary structural preparation ensures that when subsequent etching processes occur during replacement metal gate formation, the source and drain regions are already protected, preventing etching damage
Solution Approach 2:
The etch stop layer acts as an intermediary protective barrier between the source/drain regions and the etching chemicals used during replacement metal gate formation. This intermediate layer absorbs the harmful etching effects while allowing the desired gate electrode deposition to proceed
3Reliability
If gate length is increased to improve current control, then current control capability improves, but integration density decreases
Solution Approach 1:
The patent transitions from planar two-dimensional channel structures to three-dimensional nanosheet structures with vertical stacking. This dimensional change allows the gate to control current through multiple channels simultaneously, achieving superior current control capability while maintaining compact lateral dimensions that support high integration density
Solution Approach 2:
The patent implements multiple nanosheets stacked vertically within a compact footprint, creating a nested-like structure where several active channels are contained within a small area. This allows the device to achieve the current control of a longer gate while occupying the space of a much smaller device, thereby maintaining high integration density
4Reliability
If multi-gate transistor structure is used, then short channel effect is suppressed, but device structure complexity increases
Solution Approach 1:
The patent employs nanosheet structures that extend in the vertical dimension, creating multi-gate configurations where gate electrodes wrap around or contact multiple surfaces of the nanosheet channels. This three-dimensional gate control provides superior short channel effect suppression compared to planar devices, while the regular stacking pattern maintains manufacturing feasibility
Data Source
AI summary
A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region and that extends in a first horizontal direction, a second active pattern on the second region and that extends in the first horizontal direction, a first etch stop layer on the first active pattern, a second etch stop layer on the second active pattern, a plurality of first nanosheets on the first etch stop layer and that are stacked in a vertical direction and include silicon germanium (SiGe), a plurality of second nanosheets on the second etch stop layer and that are stacked in the vertical direction, a first gate electrode on the first etch stop layer and that extends in a second horizontal direction, and a second gate electrode disposed on the second etch stop layer and that extends in the second horizontal direction.