Overshoot Current Detection Circuit for EFT-Resistant Transceivers
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Solution Overview
Problem
Wireline transceivers in applications like motor encoders face interference from electrical fast transients (EFT) that cause spikes in voltage and current, leading to missed bits and impaired operation due to the shunting action of silicon controlled rectifiers (SCRs) during overshoot periods, which prevent the generation of differential voltage.
Innovation Solution
The implementation of overshoot current detection circuits comprising transistors, current mirrors, comparators, and biasing sub-circuits that detect positive and negative overshoot currents and generate signals to adjust driver operations, ensuring reliable data transmission by boosting current and overriding comparator outputs during overshoot periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clamping circuit sinks the overshoot current during the overshoot period, then the voltage on the bus line is clamped below the SCR triggering voltage, but the driver cannot generate differential voltage on the bus line resulting in missed bits
Solution Approach 1:
The detection circuit proactively identifies the overshoot period by monitoring bus line voltage and current conditions. When an EFT event is detected and the bus voltage falls below the SCR triggering voltage, the system immediately activates the differential voltage suppression mechanism, preventing the driver from attempting to generate differential voltage during the critical overshoot period when the clamping circuit is active.
Solution Approach 2:
The system continuously monitors the bus line voltage and clamping circuit status, using this feedback to dynamically control the driver output. When the detection circuit determines that the clamping circuit is actively sinking overshoot current, it provides feedback to suppress the driver's differential voltage generation, and normal operation resumes when the overshoot condition clears.
2Object-affected harmful factors
If the SCR shunts the load to ground in response to voltage greater than triggering voltage, then EFT voltage spikes are suppressed, but the shunting action prevents proper signal transmission during the event
Solution Approach 1:
The detection circuit acts as an intermediary between the SCR clamping circuit and the driver. It monitors the effects of the SCR shunting action and mediates the driver's response by suppressing differential voltage generation during the overshoot period, ensuring that the driver does not attempt to transmit signals when the bus line is being actively clamped.
Solution Approach 2:
The system applies preliminary anti-action by suppressing the driver output before potential signal corruption can occur. When the detection circuit identifies that the SCR has activated and is shunting the load, it preemptively prevents the driver from generating differential voltage that would be corrupted by the shunting action.
3Object-affected harmful factors
If the EFT strike causes sudden spikes in current and voltage, then the bus line experiences transient interference, but the interference corrupts other digital or analog signals and impairs operation of other circuits on the IC
Solution Approach 1:
The detection circuit extracts and isolates the EFT event detection function from the main driver operation. By separately monitoring bus voltage and current conditions to identify EFT events, the system can independently control the driver response without affecting other IC circuits, containing the EFT impact to the communication interface while preserving other circuit operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains reliable data transmission during EFT events by detecting overshoot currents and adjusting driver operations, preventing missed bits and ensuring continuous communication despite external interferences.
Implementation Method 1
The comparator is configured to output a signal indicative of the current from the clamping circuit being greater than a current generated by the reference current source
Implementation Method 2
The transistor is configured to be coupled to a clamping circuit and provide a current from the clamping circuit to the current mirror
Implementation Method 3
a current mirror coupled to the transistor
Implementation Method 4
a silicon controlled rectifier (SCR) which shunts a load on the bus line to ground in response to a voltage on the bus line being greater than a triggering voltage of the SCR
Data Source
AI summary
A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.