Separate Replacement Metal Gates for GAA nFET/pFET Integration
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Solution Overview
Problem
Conventional gate all around transistor semiconductor devices face challenges in integrating n-channel and p-channel field-effect transistors due to overlapping gate metals, which affect shielding and performance, especially as device scaling reduces gate dimensions.
Innovation Solution
The implementation of separate, non-overlapping gate all around replacement metal gates for n-channel and p-channel transistors, allowing for independent tuning of gate materials and thicknesses, using a gate-last approach and sacrificial placeholders to avoid material overlap and enhance shielding effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate metals are overlapped in conventional integration flows, then integration of nFET and pFET is achieved, but shielding effectiveness deteriorates and performance is compromised
Solution Approach 1:
The gate metal structures for nFET and pFET are segmented into separate, non-overlapping regions. Each transistor type has its own dedicated gate metal layer that does not vertically overlap with the other polarity's gate metal, eliminating shielding interference while maintaining functional integration.
Solution Approach 2:
The patent transitions from a vertical stacking approach (overlapping gate metals in the same lateral footprint) to a lateral separation approach (adjoining gate metals at the same vertical level but different lateral positions). This dimensional reorganization eliminates overlap while preserving compact integration.
2Productivity
If gate dimensions are reduced for device scaling, then device density increases, but gate metal shielding capability deteriorates
Solution Approach 1:
By segmenting the gate metal structures into separate non-overlapping regions, each gate metal layer can be independently optimized for its specific transistor type without being constrained by the need to provide shielding for the other polarity. This segmentation allows thinner gate metals to maintain adequate shielding capability for their respective devices.
Solution Approach 2:
The patent applies different gate metal configurations locally optimized for each transistor polarity. nFET gate metals are optimized for n-channel characteristics while pFET gate metals are optimized for p-channel characteristics, with each having appropriate thickness and material properties tailored to its specific function rather than using a uniform design.
3Ease of manufacture
If shared gate materials are used for both nFET and pFET, then manufacturing process is simplified, but independent optimization of gate characteristics is lost
Solution Approach 1:
The gate metal deposition process is segmented into separate steps for nFET and pFET regions. This allows different materials and thicknesses to be deposited for each transistor type while still using standard semiconductor manufacturing techniques, balancing process simplicity with material optimization.
Solution Approach 2:
Different gate materials and thicknesses are applied locally to nFET and pFET regions according to their specific electrical requirements. nFETs can use gate metals optimized for electron transport while pFETs use gate metals optimized for hole transport, achieving superior device performance without requiring entirely different fabrication flows.
Data Source
AI summary
Semiconductor devices having separate (i.e., non-overlapping) gate all around replacement metal gates are provided. In one aspect, a semiconductor device includes: a wafer; and at least a first transistor of a first polarity (e.g., a pFET) and a second transistor of a second polarity (e.g., an nFET) on the wafer, where a gate electrode of the first transistor and a gate electrode of the second transistor have a single pair of vertically adjoining sidewalls. The workfunction-setting metals employed in the gate electrodes of the first and second transistors can vary, as can the composition, thickness, etc. of the gate dielectric that is present beneath the gate electrodes. A method of fabricating the present semiconductor devices is also provided.