Flash Memory Gate Insulation Layer Thickness Control
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Solution Overview
Problem
Next-generation touch IC products require ultra high voltage (UHV) elements in the logic region of flash memory devices, necessitating a method to form a gate insulation layer with a large thickness for UHV elements, which is challenging in conjunction with forming cell elements.
Innovation Solution
A method of manufacturing a flash memory device with a split gate structure that includes multiple gate insulation layers of varying thicknesses in the high voltage, ultra high voltage, and low voltage regions, using materials like silicon oxide and polysilicon, and forming spacers and gate electrodes to achieve the required thicknesses and compositions for each region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate insulation layer with large thickness is formed for UHV elements in the logic region, then the voltage handling capability of UHV elements is improved, but the manufacturing complexity increases due to the need to accommodate both cell elements and logic elements with different gate insulation layer thickness requirements
Solution Approach 1:
The substrate is divided into distinct regions (cell region and logic region with high voltage, ultra high voltage, and low voltage sub-regions), and the gate insulation layer is segmented into multiple layers with different thicknesses for different regions. This allows each region to have the appropriate gate insulation layer thickness for its specific voltage requirements without affecting other regions.
Solution Approach 2:
Different gate insulation layer thicknesses are applied to different regions of the substrate based on their specific voltage requirements. The ultra high voltage region receives the thickest gate insulation layer, the high voltage region receives a medium thickness, and the low voltage region receives the thinnest, optimizing each region's performance for its intended function.
2Reliability
If multiple gate insulation layers with varying thicknesses are formed for different voltage regions, then the performance of UHV elements is enhanced, but the number of manufacturing steps increases
Solution Approach 1:
Multiple gate insulation layers are formed using a combination of deposition and spacer formation techniques. The spacer layer is formed conformally over the substrate and then anisotropically etched to create the stepped structure, merging multiple functions (thickness control, region definition, and structure formation) into a single process sequence.
Solution Approach 2:
The spacer layer is formed in advance before the final gate electrode structure is created. This preliminary spacer formation establishes the thickness profile for subsequent gate insulation layer deposition, allowing precise control of final thicknesses without requiring multiple separate deposition steps for each region.
3Manufacturing precision
If a spacer layer is formed and etched to create spacers on sidewalls and gate insulation layer patterns, then the gate insulation layer thickness is precisely controlled for different regions, but the manufacturing process complexity increases
Solution Approach 1:
The spacer layer structure serves multiple functions simultaneously: it acts as a thickness reference for gate insulation layer deposition, defines the boundaries between different voltage regions, and creates the stepped profile needed for region-specific thickness control. The structure essentially defines its own configuration through self-aligned processes.
Solution Approach 2:
The spacer layer and its etched features serve multiple purposes in the manufacturing process: they provide thickness control references, define region boundaries, support gate electrode formation, and create the final thickness profile. A single structural element performs multiple critical functions that would otherwise require separate components or steps.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.