Triple-Well eFuse Layout Sharing Space With Programming FET
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Solution Overview
Problem
Existing eFuse layouts in triple-well regions require a large chip area, consuming up to 12% of the chip space, which is inefficient for dynamic reprogramming of computer chips.
Innovation Solution
A silicide polysilicon eFuse structure is integrated within a triple-well region, sharing the same space as a programming FET and tie-down diode, allowing for compact design and area savings by using shallow trench isolation and photolithographic processes for fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If eFuse is implemented in traditional layout, then eFuse functionality is achieved, but chip area consumption increases (up to 12% of chip area)
Solution Approach 1:
The patent combines the eFuse structure with the triple-well region structure, placing the eFuse within the same bounded region that contains the programming FET and tie-down diode. This merging of functions into a shared bounded region significantly reduces the area required for eFuse implementation while maintaining all necessary functionalities.
Solution Approach 2:
The bounded region serves multiple functions simultaneously: it contains the programming FET for dynamic reprogramming, the tie-down diode for plasma charging prevention, and the eFuse for circuit configuration. This multi-functionality within a single bounded region maximizes space utilization and reduces overall chip area consumption.
2Reliability
If eFuse uses silicon or metal traces, then eFuse operation is enabled, but trace weakness increases leading to higher failure risk
Solution Approach 1:
The patent employs silicide polysilicon for the eFuse traces, creating a composite material structure that combines the electrical conductivity of metal with the structural strength of polysilicon. This composite approach enables the traces to be both operationally functional and mechanically robust, reducing failure risk while maintaining eFuse functionality.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.