Oxide TFT Multi-Channel Structure for Pixel Redundancy
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Solution Overview
Problem
Conventional pixel structures with redundancy in thin-film transistors occupy large areas, reducing the effective pixel area and luminance in display devices.
Innovation Solution
The implementation of a thin-film transistor structure with an oxide semiconductor layer, a gate insulating layer, a gate electrode, source and drain electrodes, and n metal layers across the oxide semiconductor layer, creating (n+1) channel regions between the electrodes, allowing for redundancy without physical separation, thus reducing the transistor's size and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pixel structures with redundancy in thin-film transistors are used, then reliability is improved, but area occupied by the transistor increases
Solution Approach 1:
The oxide semiconductor layer is segmented into multiple channel regions by introducing metal layers that contact the oxide semiconductor layer. This segmentation creates multiple independent conduction paths within a single transistor structure, providing redundancy without requiring multiple separate transistors. The channel regions are divided by the metal layers disposed across the oxide semiconductor layer between source and drain electrodes.
Solution Approach 2:
The invention transitions from a planar single-channel structure to a multi-layered vertical structure by inserting metal layers within the oxide semiconductor layer. This dimensional change allows multiple channel regions to be stacked vertically, increasing functionality and redundancy while reducing the horizontal area occupied by the transistor.
2Reliability
If conventional pixel structures with redundancy in thin-film transistors are used, then reliability is improved, but luminance decreases
Solution Approach 1:
The invention merges multiple channel regions into a single integrated transistor structure rather than using separate transistors. The multiple metal layers and channel regions are combined within one transistor, providing redundancy while maintaining a compact footprint that preserves pixel luminance.
Solution Approach 2:
By moving the redundancy implementation to the vertical dimension through stacked metal layers and channel regions, the horizontal area is minimized. This allows the pixel to maintain its size and luminance while incorporating redundant conduction paths for improved reliability.
3Area of stationary object
If thin-film transistor size is reduced, then area occupied is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The oxide semiconductor layer serves multiple functions: it forms the active channel region, provides insulation between metal layers, and enables multiple conduction paths. This multi-functionality reduces the number of separate components needed, simplifying the manufacturing process and reducing precision requirements despite the compact size.
Solution Approach 2:
The transistor uses composite material structures, particularly the oxide semiconductor layer combined with metal layers. This composite approach allows for integrated fabrication processes where materials are deposited and patterned together, reducing the number of separate manufacturing steps and precision requirements.
Data Source
AI summary
A semiconductor device includes a thin-film transistor. The thin-film transistor comprises an oxide semiconductor layer, a gate insulating layer, a gate electrode overlapped on the oxide semiconductor layer through the gate insulating layer, a source electrode in contact with the oxide semiconductor layer, a drain electrode in contact with the oxide semiconductor layer and n (n is a natural number) metal layer(s) in contact with the oxide semiconductor layer and disposed across the oxide semiconductor layer between the source electrode and the drain electrode. The oxide semiconductor layer has (n+1) channel regions between the source electrode and the drain electrode in a plan view.