Isolated Floating Diffusion Pixels for Low-Noise Image Sensors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional CMOS image sensors face challenges in reducing 1/f noise and random telegraph noise due to capacitive coupling between the floating diffusion and transfer gate, limiting the minimum settling time and increasing readout noise, especially in low-light and photon-counting applications.

Innovation Solution

Incorporating a doped pinning region adjacent to the floating diffusion to reduce effective capacitive coupling between the floating diffusion and the transfer gate, and optionally the reset gate, to create a pinned transfer gate and/or reset gate, which isolates the charge transfer path from the surface region, thereby reducing overlap parasitic capacitance and feed-through voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional CMOS image sensors are used with standard floating diffusion structures, then the device complexity is low and manufacturing is easier, but the readout noise increases and noise reduction capability deteriorates due to capacitive coupling between floating diffusion and transfer gate

Engineering Contradiction:
Improvenoise reduction capabilityVSAvoidpixel structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The pixel structure is segmented by introducing an isolation region that physically divides the floating diffusion from the transfer gate, separating the capacitive coupling path and reducing noise interference

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An isolation region is introduced as an intermediary element between the floating diffusion and transfer gate, acting as a mediator to reduce direct capacitive coupling while maintaining device functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the settling time is reduced to improve readout speed, then the productivity increases, but the noise from 1/f and random telegraph noise increases because there is insufficient time for noise filtering

Engineering Contradiction:
Improvereadout speedVSAvoidnoise level
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The isolation region is pre-configured in the pixel structure to reduce capacitive coupling before readout operations begin, enabling faster settling times without sacrificing noise reduction capability

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If the capacitive coupling between floating diffusion and transfer gate is reduced, then the feed-through voltage decreases and conversion gain improves, but the device structure becomes more complex requiring additional isolation structures

Engineering Contradiction:
Improveconversion gainVSAvoidisolation structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The isolation region is strategically placed only in the critical area where capacitive coupling occurs between the floating diffusion and transfer gate, providing local noise reduction without requiring complete structural redesign

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The isolation region extends into the substrate depth dimension, utilizing the vertical space to reduce capacitive coupling without increasing lateral footprint or complicating planar device layout

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables shorter correlated double sampling times, lower noise, and higher conversion gain by minimizing feed-through voltage, leading to improved low-noise and high-speed image sensing capabilities.

Implementation Method 1

capacitive coupling between the floating diffusion and transfer gate

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Implementation Method 2

reduce overlap parasitic capacitance

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS12015862B2Image sensor having pixels with isolated floating diffusions
Publication Date: 2024.06.18 GIGAJOT TECHNOLOGY INC
  • US12015862B2 patent drawing
  • US12015862B2 patent drawing
  • US12015862B2 patent drawing

AI summary

According to some embodiments, an image sensor pixel includes a floating diffusion, a transistor gate configured to transfer charge with respect to the floating diffusion, and a doped pinning region disposed between the floating diffusion and the transistor gate, to reduce or eliminate the effective capacitive coupling between the floating diffusion and the transistor gate. The transistor gate may be an in-pixel transfer gate configured to selectively transfer photocharge from an in-pixel charge accumulation region to the floating diffusion. Alternatively, or additionally, the transistor gate may be an in-pixel reset gate configured to selectively reset the electrostatic potential of the floating diffusion.