Hybrid Nanosheet FET Structure with Dummy Layer S/D Overlap
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Solution Overview
Problem
Existing nanosheet field-effect transistors (NS FETs) face limitations in gate control and scaling capabilities, leading to inefficiencies in integrated circuit (IC) manufacturing, particularly at smaller technology nodes where off-state current and short-channel effects are significant.
Innovation Solution
A method for fabricating semiconductor devices involving the formation of multi-layer structures with alternating non-channel and channel layers, including the use of anti-punch-through layers and epitaxial S/D features, to optimize gate-channel coupling and reduce parasitic capacitance, allowing for improved gate control and increased current conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing nanosheet FET structures are used, then manufacturing is simpler, but gate control is insufficient and off-state current is high
Solution Approach 1:
The channel region is segmented into multiple thin nanosheets stacked vertically, with each nanosheet providing a separate conduction path. This segmentation enables the gate to control multiple channels simultaneously, significantly improving gate control and reducing off-state current through better electrostatic control of each individual nanosheet.
Solution Approach 2:
The device transitions from a planar two-dimensional channel to a three-dimensional stacked nanosheet structure. The gate wraps around the nanosheets in a gate-all-around configuration, providing control from top, bottom, and sidewalls. This dimensional change enables superior gate control and reduces short-channel effects.
2Reliability
If gate-all-around nanosheet structures are implemented, then gate control improves, but parasitic capacitance increases
Solution Approach 1:
The device incorporates regions with different numbers of nanosheets (e.g., first region with more nanosheets than second region) to locally optimize performance. Areas requiring high current conduction have more nanosheets, while areas requiring low parasitic capacitance have fewer nanosheets, allowing simultaneous optimization of both parameters in different locations.
Solution Approach 2:
The patent varies the number of nanosheets, their thickness, and doping concentrations as adjustable parameters to optimize the balance between gate control, current conduction, and parasitic capacitance. By changing these parameters, the device can be tuned for specific application requirements.
3Productivity
If technology node scaling continues, then production efficiency increases and costs decrease, but off-state current and short-channel effects worsen
Solution Approach 1:
As technology nodes scale down, the patent employs vertically stacked nanosheets to maintain effective channel control. The gate-all-around structure provides control from all directions, preventing short-channel effects that typically worsen with scaling. This 3D architecture allows continued scaling while maintaining low off-state current through superior electrostatic control.
Data Source
AI summary
A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.