Trench-Gate 2D Semiconductor Layout for Low-Resistance Contacts
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization due to performance degradation and contact resistance issues, particularly when using two-dimensional (2D) materials, which limit their integration and efficiency.
Innovation Solution
A semiconductor device design featuring a trench structure with a gate electrode, a 2D semiconductor channel layer, and electrodes, where the trench width varies continuously with depth, and the electrodes are positioned to minimize contact resistance, utilizing transition metal dichalcogenide (TMD) materials and specific deposition processes like vapor deposition and physical vapor deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are miniaturized to increase integration density, then degree of integration is improved, but contact resistance increases and performance degrades
Solution Approach 1:
The patent introduces a trench structure that extends vertically into the substrate, adding a depth dimension to the electrode contact path. This allows the electrode to reach the channel layer at a deeper level, creating a three-dimensional contact geometry that reduces contact resistance while maintaining a compact planar footprint for high integration density.
Solution Approach 2:
The electrode is positioned within the trench structure, with the channel layer nested around the electrode in the trench. This nested arrangement maximizes the contact area between the electrode and channel layer within a confined space, reducing contact resistance without increasing the device's planar dimensions.
2Productivity
If trench width is reduced to increase integration density, then degree of integration is improved, but channel length becomes insufficient
Solution Approach 1:
The channel layer is configured to extend along the trench walls and bottom, utilizing the vertical depth of the trench to provide sufficient channel length. This transforms the channel path from a purely planar two-dimensional path to a three-dimensional path that exploits the trench depth, maintaining adequate channel length while minimizing the planar footprint.
Solution Approach 2:
The trench has a curved profile with specific inclination angles (greater than 0° and less than or equal to 45°), and the channel layer conforms to this curved geometry. This curved configuration optimizes the channel path length within the constrained trench width, providing sufficient effective channel length for device performance while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the integration and performance of semiconductor devices by reducing contact resistance and maintaining sufficient channel length, enabling improved current delivery and higher density integration without performance degradation.
Implementation Method 1
utilizing transition metal dichalcogenide (TMD) materials and specific deposition processes like vapor deposition and physical vapor deposition
Implementation Method 2
utilizing transition metal dichalcogenide (TMD) materials and specific deposition processes like vapor deposition and physical vapor deposition
Data Source
AI summary
A semiconductor device includes a substrate including a gate electrode therein, a trench penetrating the gate electrode and arranged in the substrate, a gate insulating layer in the trench and an upper surface of the substrate, a channel layer on the gate insulating layer and including a two-dimensional (2D) semiconductor material, and a source electrode and a drain electrode, which are spaced apart from each other on the channel layer.