Tri-gate Multi-nanowire Transistor with Graded III-N Layers

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Solution Overview

Problem

Current III-N materials-based transistor devices face challenges in achieving increased drive current, improved gate control, and reduced leakage at a given dimension, which are crucial for high-performance power management and radio frequency integrated circuits.

Innovation Solution

The implementation of a transistor structure with a fin structure featuring interleaved graded III-N material layers and polarization layers, where the graded III-N material layers have a decreasing indium concentration profile along the height, providing a multi-gate architecture and a carrier gas for enhanced electron transport.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional transistor structures are used, then device simplicity is maintained, but drive current is insufficient and gate control is weak

Engineering Contradiction:
Improvedrive currentVSAvoidtransistor structure complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with multi-gate control. The nanowire configuration enables gate control from multiple directions (top, bottom, and sidewalls), fundamentally changing the dimensional approach to achieving better gate control and drive current without simply scaling down lateral dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite material structures including III-N material layers (such as GaN, AlN, InGaN) combined with polarization layers and graded concentration profiles. These composite material systems leverage the wide bandgap properties of III-N materials while using polarization effects and compositional gradients to enhance carrier concentration and control electrical characteristics, thereby improving drive current and reducing leakage.

Inventive Principle:
Principle #40Composite materials

2Productivity

If device dimensions are reduced to improve integration, then form factor is improved, but leakage increases and drive current decreases

Engineering Contradiction:
Improveintegration densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent utilizes parameter changes in material composition through graded III-N material layers where the indium concentration varies continuously or in steps. This compositional gradient allows tuning of bandgap energy, carrier concentration, and polarization effects to optimize the balance between drive current and leakage current. The graded structure enables maintaining low leakage while preserving high drive current capability in scaled devices.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality variations through graded concentration profiles of indium in III-N material layers. Different regions of the nanowire structure have different material compositions optimized for specific functions: higher indium content regions for carrier generation, lower indium content regions for low leakage, and intermediate regions for transport. This spatial variation in material quality enables simultaneous optimization of drive current and leakage suppression.

Inventive Principle:
Principle #3Local quality

3Power

If conventional material systems are used, then manufacturing simplicity is maintained, but gate control and drive current are insufficient

Engineering Contradiction:
Improvedrive currentVSAvoidmanufacturing complexity
Core Design Contradiction:
PowerVSEase of manufacture

Solution Approach 1:

The patent employs parameter changes in material composition through graded III-N material layers where the indium concentration varies continuously or in steps. This compositional gradient allows tuning of bandgap energy, carrier concentration, and polarization effects to optimize the balance between drive current and leakage current. The graded structure enables maintaining low leakage while preserving high drive current capability in scaled devices.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures including III-N material layers (such as GaN, AlN, InGaN) combined with polarization layers and graded concentration profiles. These composite material systems leverage the wide bandgap properties of III-N materials while using polarization effects and compositional gradients to enhance carrier concentration and control electrical characteristics, thereby improving drive current and reducing leakage.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances drive current and gate control while reducing leakage, leading to improved performance in III-N materials-based transistors for power management and radio frequency applications.

Implementation Method 1

interleaved graded III-N material layers and polarization layers, where the graded III-N material layers have a decreasing indium concentration profile along the height, providing a multi-gate architecture and a carrier gas for enhanced electron transport

Methodology Applied
Scientific EffectPolarization: Polarisation

Data Source

PatentUS11387329B2Tri-gate architecture multi-nanowire confined transistor
Publication Date: 2022.07.12 INTEL CORP
  • US11387329B2 patent drawing
  • US11387329B2 patent drawing
  • US11387329B2 patent drawing

AI summary

Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.