Vertically Offset Nanosheet Stacks for Block-Level GAA Tuning
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating Gate-All-Around (GAA) devices as feature sizes and spacing decrease, limiting device flexibility and performance across different applications due to the use of a uniform number of nanosheets across the entire chip or wafer, which restricts power, performance, area, and cost (PPAC) improvements.
Innovation Solution
The implementation of semiconductor structures with varying numbers and widths of nanosheets across a single chip or wafer, allowing for customizable nanosheet stacks tailored to specific functional blocks, enabling adjustable power consumption and performance to match different design specifications, such as System-on-Chip (SoC), Central Processing Units (CPU), Graphic Processing Units (GPU), and High-Performance Computing (HPC) elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a uniform number of nanosheets is used across the entire chip or wafer, then fabrication process simplicity is maintained, but device flexibility and performance optimization for different applications are limited
Solution Approach 1:
The fabrication process is segmented into multiple stages: forming recessed regions with different depths, depositing nanosheet stacks, and selectively removing nanosheets in different regions. This segmentation enables different functional blocks to have different numbers of nanosheets while using a systematic fabrication approach
Solution Approach 2:
Different regions of the chip are given different local qualities by controlling the number of nanosheets in each region. Recessed regions with greater depth retain more nanosheets after selective removal, while regions with lesser depth have fewer nanosheets, optimizing performance for specific functional blocks
2Quantity of substance
If feature sizes and spacing are decreased to increase device density, then higher device density is achieved, but fabrication challenges increase
Solution Approach 1:
The patent introduces vertical dimensionality by creating recessed regions at different depths in the substrate. This vertical segmentation allows differentiation of functional blocks without increasing lateral feature density, thereby maintaining fabrication ease while achieving higher effective device density through three-dimensional structuring
3Use of energy by moving object
If the number of nanosheets is varied across different functional blocks, then power consumption and performance can be optimized, but manufacturing complexity increases
Solution Approach 1:
The substrate is pre-prepared with recessed regions of different depths before nanosheet deposition. This preliminary action establishes the framework for variable nanosheet counts, allowing subsequent selective removal to create different functional blocks with optimized power consumption without requiring complete redesign of the manufacturing process
Solution Approach 2:
The patent changes the parameter of nanosheet count across different regions by controlling recess depth and selectively removing nanosheets. This parameter variation enables optimization of power consumption for different functional blocks (e.g., CPU vs. GPU vs. HPC elements) while using a standardized fabrication approach
Data Source
AI summary
Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.