Backside-Formed FinFET Airgap Spacers for Gate Capacitance Reduction
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Solution Overview
Problem
The reduction in size of FinFET components leads to increased parasitic characteristics, particularly gate-to-source/drain capacitance, which affects the operational speed and energy consumption of integrated circuits, and existing technologies struggle to effectively manage these factors.
Innovation Solution
The implementation of airgap spacers in the transistor structure, specifically forming gate and fin airgap spacers during the semiconductor fabrication process, which reduces capacitance and improves device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If FinFET components are reduced in size to increase integration density, then device miniaturization is achieved, but parasitic capacitance increases and operational speed decreases
Solution Approach 1:
The patent extracts the dielectric material from the spacer region between gate and source/drain, replacing it with an airgap. This removes the source of parasitic capacitance while maintaining the necessary structural spacing, directly addressing the harmful capacitance effect without increasing device footprint.
Solution Approach 2:
The patent changes the dielectric parameter of the spacer from a solid dielectric material to air (vacuum), which has a dielectric constant of approximately 1. This parameter change dramatically reduces the capacitance value while maintaining the same physical dimensions, resolving the contradiction between miniaturization and parasitic capacitance.
2Productivity
If FinFET components are reduced in size, then integration density increases, but gate-to-source/drain capacitance increases affecting operational speed
Solution Approach 1:
By extracting the dielectric material and creating an airgap spacer, the patent eliminates the parasitic capacitance that limits operational speed. This allows the device to maintain high integration density while restoring faster switching speeds by removing the capacitive loading effect.
Solution Approach 2:
Changing the spacer material parameter from solid dielectric to air fundamentally alters the electrical characteristics, reducing capacitance and thereby improving operational speed without sacrificing integration density achieved through miniaturization.
3Strength
If traditional dielectric spacers are used, then structural support is provided, but parasitic capacitance increases energy consumption
Solution Approach 1:
The patent removes the dielectric material that causes energy loss through parasitic capacitance, replacing it with airgap while maintaining structural support through alternative means such as the gate structure itself and surrounding dielectric layers, thereby reducing energy consumption.
Solution Approach 2:
By changing the spacer from solid dielectric to airgap, the electrical parameter of capacitance is dramatically reduced, which directly lowers the energy consumption associated with charging and discharging the parasitic capacitance during switching operations.
Data Source
AI summary
A semiconductor structure includes a substrate and a field effect transistor disposed on the substrate. The field effect transistor includes a vertical fin, source and drain regions separated by a gate region, a gate structure disposed over the gate region and a gate airgap spacer at least partially disposed about the gate structure.