Integrated Nanosheet FET and Floating Gate Memory Fabrication
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Solution Overview
Problem
The existing fabrication processes for system-on-a-chip devices require separate and complex steps for forming nanosheet FETs and floating gate memory cells, leading to increased time and resource consumption.
Innovation Solution
A method is introduced that concurrently forms nanosheet FETs and floating gate memory cells at a common die level, sharing fabrication steps such as forming a nanosheet stack, creating tunneling and floating gate layers, and replacing dummy gates with metal gates, thereby simplifying the process and reducing the number of necessary fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate fabrication processes are used for nanosheet FETs and floating gate memory cells, then each device type can be optimized independently, but the overall fabrication time and process complexity increase
Solution Approach 1:
The patent combines the fabrication processes for nanosheet FETs and floating gate memory cells into a single integrated process. Common steps including nanosheet stack formation, tunneling oxide deposition, floating gate formation, and metal gate replacement are merged into shared process sequences, reducing overall fabrication complexity while maintaining device-specific optimization through selective processing steps
2Manufacturing precision
If separate fabrication processes are used for nanosheet FETs and floating gate memory cells, then each device type can be optimized independently, but the total fabrication time increases
Solution Approach 1:
The patent implements continuous fabrication by arranging process steps so that nanosheet FET and floating gate memory cell fabrication proceed concurrently through shared process sequences. The overlapping process architecture allows both device types to be manufactured simultaneously through common steps, eliminating idle time and reducing total fabrication duration while maintaining quality
3Productivity
If concurrent fabrication is used for nanosheet FETs and floating gate memory cells, then fabrication time and resource requirements are reduced, but process integration complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct modules: shared processes (nanosheet stack formation, tunneling oxide deposition, floating gate formation, metal gate replacement) and device-specific processes (FET channel formation, memory cell isolation). This modular segmentation manages integration complexity by organizing concurrent fabrication into manageable, independently controllable process blocks while maintaining overall efficiency
Data Source
AI summary
A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.