Segmented MEOL Strap Layout for Standard Cell Current Paths
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Solution Overview
Problem
Current semiconductor fabrication processes for integrated circuits face challenges in optimizing current flow and reducing parasitic capacitance during the middle-end-of-line (MEOL) process, which affects the operation speed and performance of semiconductor structures.
Innovation Solution
The implementation of specific semiconductor structures involving conductive metal segments and local conductive segments, along with their configurations and connections, enhances current paths and reduces parasitic capacitance by adjusting the lengths and heights of these segments, thereby improving the operation speed of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interconnection structures are used during MEOL process, then manufacturing simplicity is maintained, but current flow is insufficient and parasitic capacitance is high
Solution Approach 1:
The interconnection structure is divided into multiple conductive segments (first conductive segment, second conductive segment, third conductive segment) with different configurations. Each segment serves specific functions: the first segment provides initial conduction, the second segment (with greater height) enhances current flow, and the third segment completes the interconnection. This segmentation allows optimization of current paths while managing complexity through modular design.
Solution Approach 2:
The patent introduces vertical dimension variations by creating conductive segments at different heights within the same interconnection layer. The second conductive segment has a greater height than the first and third segments, creating a three-dimensional conductive path. This dimensional change increases current flow capacity without requiring additional lateral space, effectively resolving the contradiction between current flow improvement and structural complexity.
2Speed
If standard conductive paths are used, then manufacturing process is simple, but operation speed is limited due to high equivalent resistance
Solution Approach 1:
The patent applies local quality by creating a second conductive segment with greater height at specific locations where current flow enhancement is most needed. This localized structural modification optimizes electrical properties (reducing equivalent resistance) in critical areas without requiring complex changes throughout the entire interconnection structure, thereby maintaining ease of manufacture while improving operation speed.
Solution Approach 2:
The interconnection structure combines multiple conductive segments with different geometric properties (varying heights and configurations) to create a composite conductive system. This composite structure optimizes electrical performance by providing multiple conduction paths with different characteristics, reducing overall equivalent resistance and enhancing operation speed while remaining compatible with standard fabrication processes.
3Reliability
If conventional strap configurations are used, then manufacturing is straightforward, but parasitic capacitance impacts performance
Solution Approach 1:
The power strap is segmented into multiple conductive segments with specific configurations. The second conductive segment is positioned to provide shielding effects that reduce parasitic capacitance between adjacent conductors. This segmentation allows the structure to simultaneously maintain straightforward manufacturing processes while improving performance by minimizing capacitive coupling through strategic placement of conductive elements.
Data Source
AI summary
A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.